So do you think that my reasoning that the TLB miss penalty is simply a single cycle re-fetch penalty on the faulting instruction is correct for ALPHA_SE/TimingSimpleCPU?
On Thu, Feb 9, 2012 at 12:31 AM, Gabriel Michael Black < gbl...@eecs.umich.edu> wrote: > I believe that's correct. > > > Gabe > > Quoting Paul Rosenfeld <dramnin...@gmail.com>: > > I guess I forgot to mention in my original email that I was talking about >> alpha.... I think in FS it will vector into a PAL routine, but in SE it >> looks like it's all just faked ... >> >> On Wed, Feb 8, 2012 at 11:08 PM, Gabriel Michael Black < >> gbl...@eecs.umich.edu> wrote: >> >> There are two types of mechanisms to handle TLB misses, in hardware or in >>> software. If the ISA you're using does it in software, there's a fault >>> which makes the OS handle the miss. In that case it will take however >>> long >>> it takes the OS to get things set up again. If the miss is handled in >>> hardware, then there's a TLB walker component which does memory accesses >>> to >>> look up the entry in the page tables, and the delay is determined by >>> those >>> accesses. >>> >>> Gabe >>> >>> >>> Quoting Paul Rosenfeld <dramnin...@gmail.com>: >>> >>> Hello all, >>> >>>> >>>> I'm trying to modify the TLB code for SimpleTimingCPU, but one thing I >>>> can't seem to find is what the latency of a DTLB miss is. I found the >>>> code >>>> in NDtbMissFault->invoke() for reading the page table mapping, but I >>>> can't >>>> seem to figure out if there's any mechanism for stalling the CPU to >>>> handle >>>> the fault. >>>> >>>> Reading the wiki for the SImpleTimingCPU, it sounds like it isn't meant >>>> to >>>> model this kind of detail. So is it just a one cycle fetch penalty for >>>> handling a TLB miss? >>>> >>>> If this is the case, what's the simplest CPU model that will actually >>>> stall >>>> for TLB misses? >>>> >>>> Thanks, >>>> Paul >>>> >>>> >>>> >>> ______________________________****_________________ >>> gem5-users mailing list >>> gem5-users@gem5.org >>> http://m5sim.org/cgi-bin/****mailman/listinfo/gem5-users<http://m5sim.org/cgi-bin/**mailman/listinfo/gem5-users> >>> <ht**tp://m5sim.org/cgi-bin/**mailman/listinfo/gem5-users<http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users> >>> > >>> >>> >> > > ______________________________**_________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/**mailman/listinfo/gem5-users<http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users> >
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