[gem5-users] Question about MOESI_CMP_token

Hi all, As you know MOESI_CMP_token models a two-level cache hierarchy. I intend to simulate Intel Clovertown quad-core processor. Clovertown is a multi-packaged CMP which consists of two dual-core processors and each package has a shared L2 cache. Could you tell me Clovertown can be simulated by

[gem5-users] Question about MOESI_CMP_token

Hi all, As you know MOESI_CMP_token models a two-level cache hierarchy. I intend to simulate Intel Clovertown quad-core processor. Clovertown is a multi-packaged CMP which consists of two dual-core processors and each package has a shared L2 cache. Could you tell me Clovertown can be simulated by

[gem5-users] multi-threaded applications for ALPHA SE

Hello, As you know ALPHA SE mode is not able to run multi-threaded applications which written by PThread library. So, I wrote a simple multi-threaded application by Parmacs library, and ran the application as following: ./gem5.fast ~/gem5/configs/example/se.py -n2 -c ~/myApp But I encountered wi

Re: [gem5-users] Adding a few changes to gem5 repository

> > > > > On Wed, May 16, 2012 at 1:00 PM, Hamid Reza Khaleghzadeh < > khaleghza...@gmail.com> wrote: > >> Hello, >> >> Diff command syntax is "diff source_file modified file > path_file". >> But I review a few diff files which

Re: [gem5-users] move threads to another cpu

> gem5-users mailing list > > gem5-users@gem5.org > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -

[gem5-users] gem5 simulation speed

Hi all, I am working on CMP scheduling. My runs must be long, so I need a simulator which it's simulation speed is high. Therefore, I want to know how many instructions per second can Gem5+ruby simulate? Thanks ___ gem5-users mailing list gem5-users@gem

Re: [gem5-users] Question about inter-chip network

Thanks for your answer but my general field is software. If possible please explain your answer. Best Regards On Fri, Jul 15, 2011 at 11:16 PM, Nilay wrote: > On Thu, July 14, 2011 6:56 am, Hamid Reza Khaleghzadeh wrote: > > Hi > > > > I arrived conclusion that data is be

[gem5-users] L2 miss latency

Hi I want to change L2 miss and hit latency in Gem5. Could you tell me how I can do this? by the way, Used coherency protocol is MOESI-CMP-directory. Thanks -- Hamid Reza Khaleghzadeh ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org

Re: [gem5-users] L2 miss latency

Hi Thanks for your fast reply but I cannot find any fields about miss/hit latency for L2 cache. On Tue, Aug 2, 2011 at 10:23 AM, Hamid Reza Khaleghzadeh < khaleghza...@gmail.com> wrote: > Hi > > I want to change L2 miss and hit latency in Gem5. Could you tell me how I > can d

[gem5-users] obtaining number of folating point operations

Hi all, I want to obtain number of floating point operations that occurs in the executed application, but cannot find any field in stat file that determine this parameter. Could you tell e how i can get it? Thanks. ___ gem5-users mailing list gem5-users

[gem5-users] disable Cache to cache connection in Gem5

Hi I have simulated a quad-core processor by Ruby that contains two L2 caches and each L2 is shared by two cores and coherency protocol is MOESI-CMP-directory. I found that when a data misses in one of the L2 caches and this data exists in another L2, the data is read via L2 cache_to_L2 cache inst

[gem5-users] Alpha or x86

Hi all, I am Gem5 beginner. I want to simulate a multi-core processor which is composed of two dual core CMPs (bellow schema). Could you tell me I need to use Alpha or x86 implementation of Gems5 for simulating the described architecture? By the way, coherency protocol would be considered MOESI-CM

[gem5-users] FS or SE and Alpha or x86

11.10 x86. Sorry to bother you. -- Hamid Reza Khaleghzadeh ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Installing Gem5

Hi I am Gem5 beginner. Could you tell me where I can find a manual which explains installing of Gem5? Thanks -- Hamid Reza Khaleghzadeh ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Question about Gem5 Coherency protocols

Hi I have read Gem5's documents. I found that each coherency protocol works with some architectures. Could you help me where I can find some information about it? Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/li

[gem5-users] Running Gem5 in ALPHA_FS Mode

Hi all, I have Installed Gem5 in ALPHA_FS mode, and tried to run it by following command: ./gem5.opt ~/gem5/configs/example/fs.py Simulation is continued until "warn: Prefetch instructions in Alpha do not do anything" is shown on terminal and then it doesn't do any thing. Could you tell me how I

[gem5-users] Accessing hard disk from Gem5

Hi all, I want to access to all files and folders which exist in my computer form Gem5(ALPHA_FS). Could you tell me how I can do it? Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Run a c Application in ALPHA_FS

Hi all, I have written a simple C application and then compiled with arm-linux-gnueabi-gcc. Then tried to run this application on Gem5(ALPHA_FS) but I encountered with an ERROR: modprobe: FATAL: Could not load /lib/modules/2.6.13/modules.dep: No such file or directory modprobe: FATAL: Could not

[gem5-users] X86_FS in Gem5

I want to work on CMP cache coherency protocols. I found that Gem5 developers have tested Gem5 for ALPHA target (It can be found from http://www.gem5.org/Status_Matrix). Could you tell me X86_FS has been implemented correctly and is reliable? Sorry to bother you. __

[gem5-users] Simulating Intel Clovertown in

-- Hamid Reza Khaleghzadeh ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Simulating Intel Clovertown with Gem5

Hello I want to simulate Intel Clovertown multicore processor with Gem5 (Following schema) P0 P1 P2 P3 |_| |_| | | L2L2 |_| | Memory Each processor has one

[gem5-users] Shared L2 cache

Hello Could you tell me how a L2 cache can be shared between each 2 processors (cores)? Suppose that there are 4 cores and 2 L2 caches. if I run Gem5 as bellow, can I implement the considered architecture? ./build/ALPHA_FS/m5.opt configs/example/ruby_fs.py -n 4 --l1i_size=32kB --l1d_size=32kB --l

[gem5-users] Implementing new topology in Gem5

Hello Gem5, I have implemented a network topology and then copy its python file into "~/gem5/src/mem/ruby/network/topologies/MyTopology.py". When gem5 is executed, I encounter with this error: ImportError: No module named MyTopology Could you help me? Thanks

[gem5-users] a Question

In Gems simulator, there is g_PROCS_PER_CHIP parameter that sets number of cpu per chip. Is there any similar parameter in Gem5 Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] a Question

In Gems simulator, there is g_PROCS_PER_CHIP parameter that sets number of cpu per chip. Is there any similar parameter in Gem5? Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] what is -n option

Could you tell me what is -n option in Gem5 and what difference has with --num-cpus? Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Fwd: Simulating Intel Clovertown with Gem5

Hello mahmood, I want to simulate Intel Clovertown multicore processor with Gem5 (Following schema). This processor consists of two packages that each package has two cores. P0 P1 P2 P3 |_| |_| | | L2L2

[gem5-users] a question

Could you tell what architecture this command simulates? ./build/ALPHA_FS/m5.opt configs/example/ruby_fs.py -n 16 --l1i_size=32kB --l1d_size=32kB --l2_size=32MB --num-l2caches=4 --topology=Crossbar --timing I think this command simulate a multi-core processor that consists of 4 package. Each pac

[gem5-users] L2 cache information

Hi all, I can not find any information about L2 cache, L2 cache to network connection and ... in config.ini file. Could you tell me where I can obtain these information? thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mai

Re: [gem5-users] L2 cache information

No, I don't have. On Tue, Jan 3, 2012 at 12:58 PM, Mahmood Naderan wrote: > Don't you have > [system.l2] > type=BaseCache > > ? > > On 1/3/12, Hamid Reza Khaleghzadeh wrote: > > Hi all, > > > > I can not find any information about L2 cac

Re: [gem5-users] L2 cache information

Which python file? Can you explain your answer? On Tue, Jan 3, 2012 at 1:18 PM, Mahmood Naderan wrote: > so you have not defined any L2Cache() in your python file > > On 1/3/12, Hamid Reza Khaleghzadeh wrote: > > No, I don't have. > > > > On Tue, Jan 3, 2

Re: [gem5-users] L2 cache information

. > > On 1/3/12, Hamid Reza Khaleghzadeh wrote: > > Which python file? Can you explain your answer? > > > > On Tue, Jan 3, 2012 at 1:18 PM, Mahmood Naderan >wrote: > > > >> so you have not defined any L2Cache() in your python file > >> >

Re: [gem5-users] L2 cache information

Dear Mahmood, I have a request and wuold be thankful if answer me. If possible please send me one of the config file that contains L2 cache. Thanks On Tue, Jan 3, 2012 at 1:40 PM, Hamid Reza Khaleghzadeh < khaleghza...@gmail.com> wrote: > Thank you. > > > On Tue, Jan

[gem5-users] connectAllPorts() and Network

Hello In some scripts, connectAllPorts() command is used to connect cpus to L2 cache. I want to know Interchip network and networl topology where are used? ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-use

Re: [gem5-users] Implementing new topology in Gem5

Could you help me? On Tue, Jan 3, 2012 at 3:28 PM, Nilay Vaish wrote: > On Tue, 3 Jan 2012, Hamid Reza Khaleghzadeh wrote: > > Hello Gem5, >> >> I have implemented a network topology and then copy its python file into >> "~/gem5/src/mem/ruby/network/**topologi

Re: [gem5-users] Implementing new topology in Gem5

I do it, but there is still the problem. On Tue, Jan 3, 2012 at 4:48 PM, Mahmood Naderan wrote: > After this line > clover = Clovertown() > > ensure there is no > > On 1/3/12, Hamid Reza Khaleghzadeh wrote: > > I have added my topology to Sconscript but when I wan

Re: [gem5-users] Implementing new topology in Gem5

nge(num_packs))] # link counter to set unique link ids link_count = 0 On Tue, Jan 3, 2012 at 4:58 PM, Mahmood Naderan wrote: > please paste line 49 (with some line before and after) exactly from your > file > > On 1/3/12, Hamid Reza Khaleghzadeh wrote: > > I do it, b

[gem5-users] calling create_system()

Hi Gem5, I have traced ruby_fs.py execution. I found that create_system() function in this file that invokes create_System() of Rury.py and create_System() of MI_example.py. MOESI_CMP_directory.py implements create_system() function. Could you tell me how I can invoke create_system() of MOESI_CMP_

Re: [gem5-users] calling create_system()

I have done it, but create_system() of Ruby.py is invoked. On Tue, Jan 3, 2012 at 10:06 PM, Nilay Vaish wrote: > On Tue, 3 Jan 2012, Hamid Reza Khaleghzadeh wrote: > > Hi Gem5, >> >> I have traced ruby_fs.py execution. I found that create_system() function >>

Re: [gem5-users] calling create_system()

Thanks. I have already typed PROTOCOL=MOESI_CMP_directory wrong. On Wed, Jan 4, 2012 at 3:41 PM, Nilay Vaish wrote: > On Tue, 3 Jan 2012, Hamid Reza Khaleghzadeh wrote: > > I have done it, but create_system() of Ruby.py is invoked. >> >> > It is invoked, but it requ

[gem5-users] Running PThread Application in SE

in system.cpu[i].workload = multiprocesses[i] IndexError: list index out of range Could you help me? By the way, I have another question. You know that there is not any thread scheduler in SE. Is it possible that in pthread application bind threads to cores directly? Thank

[gem5-users] MOESI_CMP_directory in SE

Hi Could you tell me MOESI_CMP_directory works in SE mode? Could you tell me what Ruby option in SE mode is? ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] FS or SE

Hi I am working on CMP Scheduling Algorithms. In my case, Gem5 is used as a cmp simulator. I bind threads of multi thread applications to cores of the simulated machine manually, and compare obtained results as execution time and cache misses. By the way, In my research, coherency protocols are im

Re: [gem5-users] FS or SE

ed syscalls" errors. > > > > On 1/4/12, Hamid Reza Khaleghzadeh wrote: > > Hi > > > > I am working on CMP Scheduling Algorithms. In my case, Gem5 is used as a > > cmp simulator. I bind threads of multi thread applications to cores of > the > > simulate

[gem5-users] Pthread application in Gem5

Hi list, I found that PThread application can not be executed in SE mode. A pthread library is introduced In http://permalink.gmane.org/gmane.comp.emulators.m5.devel/2286 for Gem5. Could you tell me where I can find it? Thanks ___ gem5-users mailing lis

[gem5-users] Compiling M5thread

‘long long unsigned int’, but argument 3 has type ‘void **’ [-Wformat] ../pthread.c:476:8: warning: format ‘%llx’ expects argument of type ‘long long unsigned int’, but argument 3 has type ‘void **’ [-Wformat] make: *** [../pthread.o] Error 1 Could you help me

[gem5-users] PThread application in Gem5

Hello I am Hamid R. Khaleghzadeh and working on CMP scheduling. I use X86_SE mode to run multi-threaded benchmarks and my pthread applications. I found that X86_SE cannot run PThread application. I want to know there are any library like pthread? By the way, I found that M5thread and Parmacs libra

[gem5-users] Creating Multi-thread applications for GEM5

Hi all, X86_SE and ALPHA_SE cannot execute PThread applications. There is M5Threads library that introduced for M5 but it can be compiled for X86 and ALPHA. So, I want to know how multi-thread applications can be written for SE mode? Thanks. ___ gem5-us

[gem5-users] Parmacs

Hi Could you tell me how I can create a parallel shared memory program by parmacs for X86? Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Running Splash on Gem5

Hi I have run some benchmarks of Splash on Gem5 ALPHA_SE. When the number of cpus or threads is set more than one, I encounter with following error. Could you tell me SPLASH benchmark is runnable on ALPHA_SE? Traceback (most recent call last): File "", line 1, in File "/home/hamidreza/gem5/s

Re: [gem5-users] Running Splash on Gem5

: > What is your script? > > On 1/7/12, Hamid Reza Khaleghzadeh wrote: > > Hi > > > > I have run some benchmarks of Splash on Gem5 ALPHA_SE. When the number of > > cpus or threads is set more than one, I encounter with following error. > > Could you tell me S

Re: [gem5-users] Running Splash on Gem5

Thanks for your answer. I can execute splash benchmark with run.py. Could you tell me how I can determine network topology in this case? On Sat, Jan 7, 2012 at 11:23 PM, Mahmood Naderan wrote: > have you tried configs/splash2/run.py instead of se.py? > > On 1/7/12, Hamid Reza Khaleghzad

[gem5-users] SE and Multi-threaded app.

Hi all, I am Gem5 beginner, but I found that SE doesn't support multi-threaded applications. Also, I think that multi-threaded Splash benchmarks cannot be executed with Ruby. Are these true? Sorry to bother you. ___ gem5-users mailing list gem5-users@ge

[gem5-users] Segmentation fault when running pthread application in ALPHA_FS

Hi list, I have written a Pthread application a compiled it with gcc cross compiler and -static option. when I run this application by ALPHA_FS, I encountered with Segmentation fault error. Could you tell me how I can solve this error? Thanks ___ gem5-u

[gem5-users] Installing Gcc in ALPHA_FS

Hi all, I have written some PThread applications and compiled them with gcc cross compiler. When these applications was executed on ALPHA_FS, I encountered with Segmentation Fault error. Now, I want to install gcc on Linux Alpha and recompile my Pthread applications. Could you tell me where I can

[gem5-users] Compiling Parmacs application

Hi Could you tell me how parmacs application can be compiled? I have written a multi threaded parmacs application. When it is compiled with gcc, I encounter with following errors: /home/hamidreza/parmacs.upc.3/pthreads/parmacs.h:35:1: error: unknown type name ‘parmacs_barrier’ /home/hamidreza/pa

[gem5-users] Compiling Multi-threaded Parmacs application

Hi Could you tell me how parmacs application can be compiled? I have written a multi threaded parmacs application. When it is compiled with gcc, I encounter with following errors: /home/hamidreza/parmacs.upc.3/pthreads/parmacs.h:35:1: error: unknown type name ‘parmacs_barrier’ /home/hamidreza/pa

[gem5-users] alphaev67-unknown-linux-gnu-gcc and static linking

ction `main': (.text+0xa90): undefined reference to `pthread_join' collect2: ld returned 1 exit status -- Hamid Reza Khaleghzadeh ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] alphaev67-unknown-linux-gnu-gcc and static linking

Hi yanke, Thanks for you answer. I have used -lpthread, but problem remains. On 1/12/12, yanke wrote: > add -lpthread when compiling > > > > > > At 2012-01-12 19:52:11,"Hamid Reza Khaleghzadeh" > wrote: >>Hi all, >> >>I have written a PTh

Re: [gem5-users] alphaev67-unknown-linux-gnu-gcc and static linking

did that, but the problem remains. Could you tell me how I can solve the problem? Sorry to bother you. On 1/12/12, Eliot Moss wrote: > On 1/12/2012 10:57 AM, Hamid Reza Khaleghzadeh wrote: >> Hi yanke, >> >> Thanks for you answer. I have used -lpthread, but problem rema

Re: [gem5-users] alphaev67-unknown-linux-gnu-gcc and static linking

Excuse me, I'm again. could you tell me when libpthread.a is replaced with another one, gcc cross compiler must be created again? On 1/12/12, Hamid Reza Khaleghzadeh wrote: > Hi > > It works. I could compile the application. but when I run it in the > Gem5, I encounter with

Re: [gem5-users] alphaev67-unknown-linux-gnu-gcc and static linking

f or something underlying it (libc mismatch, system call > mismatch, etc). > > > > On Thu, Jan 12, 2012 at 11:48 AM, Hamid Reza Khaleghzadeh < > khaleghza...@gmail.com> wrote: > >> Excuse me, I'm again. could you tell me when libpthread.a is replaced >>

Re: [gem5-users] alphaev67-unknown-linux-gnu-gcc and static linking

Thanks for your answer, but could you explain your answer further? Thanks 2012/1/12 yanke > You should use the kernel on the parsec insead of the one on the m5 > website. > > > > At 2012-01-13 00:48:24,"Hamid Reza Khaleghzadeh" > wrote: > >Excuse

Re: [gem5-users] alphaev67-unknown-linux-gnu-gcc and static linking

Hi Thanks for your reply. I have replaced current kernel image with 2.6.27 one. 2012/1/13 yanke > http://www.cs.utexas.edu/~cart/parsec_m5/ > > > > At 2012-01-13 01:38:02,"Hamid Reza Khaleghzadeh" > wrote: > > Thanks for your answer, but could you expla

[gem5-users] Alpha with more than 4 cpus

Hi I need to simulate a CMP processor which consists of more than 4 cpus. I found that gem5 has implemented BigTsunami. It supports up to 64 processors. Could you tell me where I can find BigTsunami or how I can create it? Thanks ___ gem5-users mailing

[gem5-users] questions about Gem5 stat

Hi all, I use gem5 for running an application and obtain execution time and the number of L1 and L2 miss count which *only* caused by the application and occur in the execution time of the program. I have already used Simics+gems for simulation. In the Simics, there are features that allow the pro

[gem5-users] using m5op.h in C programs

Hi Assume I want to reset simulation statistics from through a C program. So, I must add m5op.h header file to the application, and call resetstats(...) function in the application. I have done it, but encountered with following error when I compiled the program. Could you tell me how facilities o

Re: [gem5-users] using m5op.h in C programs

stats' collect2: ld returned 1 exit status On Fri, Jan 13, 2012 at 5:11 PM, Hamid Reza Khaleghzadeh < khaleghza...@gmail.com> wrote: > Hi > > Assume I want to reset simulation statistics from through a C program. So, > I must add m5op.h header file to the application, and call reset

[gem5-users] using m5op.h in C Program

Dear Joel, In slide 78 of isca_pres_2011.pdf, you described instrumenting a benchmark. I have written a C program: #include #include int main() { m5_dump_stats(1,0); printf("hello world\n"); return 0; m5_dump_stats(1,0); } I have compiled this application as following: alphaev6

Re: [gem5-users] using m5op.h in C Program

and compiling with the alpha cross > compiler? Why wouldnt you use the alpha version? > > > -- > - Korey > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-

[gem5-users] Obtain L2 miss count

Hi I use ruby_fs.py script for running Gem5. Could you tell me where I can find number of L2 cache miss count? Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Number of cahce miss

Hi list, I have simulated a CMP which contains two level caches (L1 and L2). I want to know the number of cache misses that occurs in L2. Could you tell me where I can find my desired information? ___ gem5-users mailing list gem5-users@gem5.org http://m5

[gem5-users] Shared L2 cache in Gem5

Hi MOESI_CMP_directory is a coherency protocol that is used in my case. I simulate a multi-core processors which consists of 6 cores. I want to the cmp contains 3 L2 caches and each of them is shared with 2 cores. For this reason, I have implemented an intra-chip network which defines how cores mu

[gem5-users] Recording accesed data addresses

Hi I need address of all accessed data by the executed application in ALPHA_FS. I think a recording module must be added to Gem5. The recorder must be able to log threadID, data address and access type (Read/Write). I don't know where I can add this module. Could you help me? _

[gem5-users] "Ruby requires TimingSimpleCPU or O3CPU!!" ERROR

Hi all, I cannot run Gem5 by following command line becuase of encountering with "Ruby requires TimingSimpleCPU or O3CPU!!" error: ./gem5.opt ruby_fs.py -n 4 --l1i_size=32kB --l1d_size=256kB --l2_size=16MB --num-l2caches=2 Could you help me? Thanks. __

Re: [gem5-users] "Ruby requires TimingSimpleCPU or O3CPU!!" ERROR

ood Naderan wrote: > that is straight. use either detailed or timing model. If you have an > old revisiosn, --detailed and --timing are used. If you have the > latest revision, --cpu-type=detailed and --cpu-type=timing are > available. > > On 3/5/12, Hamid Reza Khaleghzadeh wrote: >

[gem5-users] New revision Gem5 problem with Ruby

Hi I have built new revision of Gem5. Now, I cannot run Gem5 by Ruby_fs.py script. I set cpu-type to 'timing' or 'detailed', but encounter with following problem. Could you help me? Sorry to bother you.

Re: [gem5-users] New revision Gem5 problem with Ruby

(self.__class__.__name__, attr) > > AttributeError: Class Bus has no parameter master_port > > > .... > > > > > -- > -- > // Naderan *Mahmood; > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Hamid Reza Khaleghzadeh ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Running New revision Gem5 by ruby_fs.py

ss__.__name__, attr) AttributeError: Class Bus has no parameter master_port Could you help me how this problem can be solved? Thanks -- Hamid Reza Khaleghzadeh hkhaleghzadeh.webs.com ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] pthread, ALPHA_SE

ulti-core ALPHA_SE system, i haven't > found how to do it. Could anyone tell me how to do it? > Thank you. > Kostadinos Parasyris > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-us

[gem5-users] Problem with FS in new revision of Gem5

Hi all, When I run the latest revision of Gem5 with ruby_fs script (ALPHA_FS), I encounter with Segmentation fault error. Could you help me how I can solve it? Thanks -- Hamid Reza Khaleghzadeh hkhaleghzadeh.webs.com ___ gem5-users mailing list gem5

Re: [gem5-users] A segmentation fault of running ruby memory model

--- > Chuanlei > > _______ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Hamid Reza Khaleghzadeh hkhaleghzadeh.webs.com ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] ERROR Checkpointing in ALPHA full system

OMIC)) { > return Event:Store; > } else { > error("Invalid RubyRequestType"); *HERE is the LINE 221 > > } > } > > > I guess this is because CPU send a wrong type of RubyRequest message > to a L1 cache and I

Re: [gem5-users] Alpha Ruby Full System: 'm5 checkpoint' Fails

Does it mean we can not take checkpoint with the ruby model full system? >> >> __**_ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/**mailman/listinfo/gem5-users<http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users> > -- Hamid Reza Khaleghzadeh hkhaleghzadeh.webs.com ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Alpha Ruby Full System: 'm5 checkpoint'

g our > desired protocol? > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Hamid Reza Khaleghzadeh hkhaleghzadeh.webs.com ___ gem5-users mailing list gem5-users@gem5.org h

Re: [gem5-users] Alpha Ruby Full System: 'm5 checkpoint'

By the way, For finding answer of your question, you can visit flowing URL: http://www.gem5.org/Cache_Coherence_Protocols On Mon, Mar 26, 2012 at 12:39 PM, Hamid Reza Khaleghzadeh < khaleghza...@gmail.com> wrote: > Sorry, I have chosen MOESI_token as coherency protocol. May I know Gem5

[gem5-users] Error in Set.cc

Hi all, There is an compile time error in Set.cc file, line 357. Please developers correct this error. Thanks. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Checkpoint in ALPHA RUBY_FS

Hi all, I found that in new revision of Gem5, m5 checkpoint doesn't work correctly. Are there any solutions for it? Thanks. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Obtain memory trace

Hi, May I know how I can modify gem5 to log address of all data which accessed by a multi-threaded program? The memory trace must contain information about thread ID, accessed memory address and Access type (read/write). Thanks for your answer in advance -- Hamid Reza Khaleghzadeh

[gem5-users] --Cahces option in Ruby

Hi list, Ruby has an option called "caches". May I know what the option is? Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] --Ruby option in Ruby

Hello, Ruby has an option called "Ruby". May I know what the option does? Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Question about debug-flags

Hi, As you know, there are various debug flags in Gem5. Could you tell me where I can find function of each of them? Best regards ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Question about debug-flags

> gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Hamid Reza Khaleghzadeh hkhaleghzadeh.webs.com ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Obtain memory trace by debug flags

Hello, I want to obtain memory trace of multi-threaded applications by Gem5. I think that Exec debug-flag can meet my need. Do you agree with me or you believe that there are better ways? Thanks for your answer in advance. ___ gem5-users mailing list ge

[gem5-users] Question about Exec debug flags

Hello, Could you tell me what the functionality of following flags is? ExecEffAddr, ExecEnable, ExecFaulting, ExecKernel, ExecMicro, ExecOpClass, ExecResult, ExecSymbol, ExecThread, ExecTicks, ExecUser. Thanks ___ gem5-users mailing list gem5-users@gem

[gem5-users] Problem with threadID

I have executed a multi-threaded application on Gem5 by Exec debug flag. In the obtained trace file, All threadIDs are T0. How do you legitimize it? ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Define new debug flag

Hi, I have added a new debug flag to Gem5. Now, Could you tell me how this flag can be accessed in source code? ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Adding new debug flag

Hi all, I have added a debug flag by adding debugflag() command to gem5/src/cpu/SConscript file. I want to use the flag in gem5/src/cpu/exetrace.cc file, But I don't know how to do it. Could you help me? Thanks ___ gem5-users mailing list gem5-users@gem

[gem5-users] Controlling debug by application

Hi all, Could you tell me how debugging in gem5 can be enabled or disabled with application? You know that there are some facilities in Gem5 for restarting and dumping stat results. Are there same facilities for gem5 debugging? ___ gem5-users mailing lis

[gem5-users] compile time error

Hi, I have updated gem5 but I cannot build it. There are following errors. Could you tell me how the problems can be solved? By the way, I have installed Gem5 on Ubuntu 11.10 (32-bit). In file included from /home/hamidreza/build/ALPHA/base/inifile.hh:40:0, from /home/hamidreza/bu

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