Hi
MOESI_CMP_directory is a coherency protocol that is used in my case. I simulate a multi-core processors which consists of 6 cores. I want to the cmp contains 3 L2 caches and each of them is shared with 2 cores. For this reason, I have implemented an intra-chip network which defines how cores must be connected to L2 caches. Is it ture? _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
