Those options are being ignored because you're not using caches at all. You
need --caches.
-Tony
On Thu, Nov 1, 2012 at 3:36 PM, Payne, Benjamin wrote:
> Hello,
>
> I am running gem5 in syscall emulation mode and specifying the cache
> sizes. This appears to work as desired.
>
> bpayne@bpayne-V
Hello,
I am running into an assertion failure, assert(!downstreamPending), in
MSHR::clearDownstreamPending(). This assert fails some of the time, but not
always. My question is, what is the difference between markedPending and
downstreamPending? It seems that marked pending is only every used insi
I have a system that repeatedly switching back and forth between core
types; I am trying to evaluate the effects on the caches due to switching.
I give each core its own L1 caches and when switching out, it keeps its L1s
connected. However, when I upgraded to the latest repo that uses simple
DRAM.
Hi Andreas,
Actually, it appears the simple_dram does not drain properly at all in some
cases. You should be able to reproduce this error using a clean checkout (I
did add DPRINTFs to simple_dram.cc:drain()) without any modifications; the
following command line is what I ran:
./build/ALPHA/m5.opt
NOTE, the problem with this trace is that it hangs while trying to drain
because the physmem never signals drained; it's dramWriteQueue is never
emptied and only refreshes forever.
-Tony
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There is a simple pipeline view in the util directory, this can be used for
debugging. Other than that, I don't know of any GUI for gem5.
-Tony
On Tue, Nov 6, 2012 at 5:33 PM, Payne, Benjamin wrote:
> Hello,
>
> I was playing around with AMD's SimNow, which has a GUI. Here are some
> examples:
The default only has a shared L2 cache. If you wanted to use private L2
caches per core you'd need to instantiate num_cores L2 caches and L2
busses, then connect them to the CPUs. E.g., you have to do something like
this:
system.ls = [ L2Cache(clock = options.clock, size=...) for i in
xrange(num_c
Yes. And I hope to add a draining regression soon.
On Nov 7, 2012 3:29 AM, "Andreas Hansson" wrote:
> Hi Tony,
>
> Could you give this one a go: http://reviews.gem5.org/r/1535/
>
> It seems to solve the problem on my end.
>
> Andreas
>
> From: Anthon
Can you provide some more information? What is your command line? Does the
simulation stop or fault? Does BBench ever start, what does the frame
buffer show?
That may be a warning that can be ignored.
-Tony
On Wed, Nov 7, 2012 at 2:42 AM, Aparna Mandke wrote:
> Hi,
> I am using ICS image and An
Hello Martin,
I am out of town at the moment. I will make my patches for the ARM kernel
available some time within a week.
-Tony
On Dec 5, 2012 10:21 AM, "Martin Brown" wrote:
> Hello Anthony,
>
> I'm a gem5 user. I'm running Android simulations. I'm trying to use the
> ProcessInfo methods, but
Here is a patch for the 2.6.38.8 kernel that adds the necessary process
information:
diff --git a/arch/arm/kernel/m5op.S b/arch/arm/kernel/m5op.S
new file mode 100644
index 000..af56bc6
--- /dev/null
+++ b/arch/arm/kernel/m5op.S
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All
Are all of your runs on the same machine and/or with the same setup? Please
provide your exact command line and system setup.
-Tony
Hi Andreas,
** **
Thank you so much for your reply. I think my hg id is 94383c5124d2+ tip.
And sadly, I don’t think it happen at the exact same tips every time
Did you look at logcat to see if it gives any hints as to what the problem
may be?
-Tony
On Mon, Jan 21, 2013 at 7:33 AM, huangyongbing wrote:
> Hi all,
>
> ** **
>
> I run bbench on arm platform using ics image downloaded from
> gem5’s website, and find that bbench stays at the fin
I am confused as to what you want to do. Do you want to run only one
webpage per run of the simulator? Or run separate instances of the browser,
each running a different page, in parallel?
In any case, if you want to eliminate any particular page from the
benchmark you need to mount the disk image
Right. But, as was also pointed out, this makes it a completely different
benchmark. Just a word of caution.
-Tony
On Wed, Jan 23, 2013 at 2:59 PM, Jack Harvard wrote:
> As somebody on the list said, you can isolate the 11 pages into 11
> parallel runs on your cluster. You need to configure the
I get an assertion failure when I repeatedly switch with the O3 CPU:
m5.opt: build/ARM/cpu/o3/fetch_impl.hh:432: void
DefaultFetch::drainSanityCheck() const [with Impl = O3CPUImpl]:
Assertion `!memReq[i]' failed.
Program aborted at cycle 10476827000
I am trying to run bbench on gingerbread with
Hi Gabriel,
I have finished a new version of BBench, version 3.0, you can get it here:
http://bbench.eecs.umich.edu
That site is still under heavy construction and I haven't officially
announced the release yet, so there isn't a ton of info; the new version is
written in html5 and is able to inte
Hi Hongyuan,
switchcpu causes simulation to exit with the cause "switchcpu", it doesn't
actually cause a CPU switch. You could do something like this: add
"/sbin/m5 switchcpu" to your rcS script before you launch your benchmark.
Then you will need to modify the Simulation.py script to recognize th
n advance!
>
>
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
> --
> Anthony Gutierrez <http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users>
> <http://m5sim.org/cgi-bin/mailman/
lso I assume the regular detailed mode is also fairly similar to modern
> OoO CPUs?
>
>
> On Thu, Feb 14, 2013 at 10:59 PM, Anthony Gutierrez wrote:
>
>> The ARM detailed CPU is just the detailed CPU with certain parameters set
>> to model a modern OoO ARM CPU.
>>
&g
image.
Simply mount the image, then copy the apk file to /system/app. If you
notice there are a few APKs that I added to the Gingerbread image,
ReplicaIsland.apk and smartbench.apk. Both worked ok with this method.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, Feb 19, 2013 at 11:16
PK is
not distributed independently by the authors, I don't know how to get
access to the APK.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, Feb 19, 2013 at 1:07 PM, Fangfei Liu wrote:
> Hi Anthony,
>
> ** **
>
> Thank you so much for your help! Do you kn
I would never advocate such things... :-P
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Wed, Feb 20, 2013 at 5:33 AM, Jack Harvard wrote:
> Why not has a try "Download AndEBench apk" into Google?
>
> Jack Harvard
>
>
> On Tue, Feb 19, 2013 at 6:16
likely to see it being used. If you run BBench, it will be used heavily.
Unless you're doing research in this specific area I wouldn't worry about
that instruction not being implemented.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, Feb 26, 2013 at 3:48 AM, Abu Saad wro
Can we push that patch out?
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, Feb 26, 2013 at 8:39 AM, WonSeob Jeong wrote:
> Hi, Korey
>
> Thank you for your help!
> I applied hwrei patch and it works fine.
>
> Won Seob Jeong
>
>
> On 02/26/2013 0
e sky for me...but it hasn't so far! :)
>
> -Korey
>
> On Tue, Feb 26, 2013 at 6:38 AM, Ali Saidi wrote:
>
>> **
>>
>> If memory serves the change breaks the o3 cpu for Alpha.
>>
>>
>>
>> Ali
>>
>>
>>
>> On 26.02.20
s@gem5.org/msg06632.html if I simply
run ./build/ARM/m5.fast configs/example/fs.py. Any help would be
appreciated.
Thanks,
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
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I tried clang, it also has linker errors. I'll try to figure out why the
llvm compiler that comes with my Xcode isn't working.
Thanks,
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Sat, Mar 2, 2013 at 10:50 AM, Ali Saidi wrote:
> HI Tony,
>
> I'm running 1
't working.
I'll have to start fresh and double check everything.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Sat, Mar 2, 2013 at 1:57 PM, Andreas Hansson wrote:
> Hi Tony,
>
> I use Xcode 4.6, and clang/clang++ as the default compiler (clang
> 3.2svn).
>
&
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Sat, Mar 2, 2013 at 10:38 PM, Hossein Nikoonia wrote:
> I did this in Lion without a problem. Maybe you have multiple versions of
> gcc and that is confusing ...
>
>
> On Sat,
Bytes.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Mon, Mar 4, 2013 at 3:03 PM, Ding, Hongyuan wrote:
> Hi all,
> I use the option of --cacheline_size=64 to define cache block size
> for dcache. But I wonder 64 means 64bits or 64bytes.
> Can an
If you have the cds then you have the source and can build them yourself.
The binaries may not be distributed.
On Mar 8, 2013 4:52 PM, "Xiaobin Liu" wrote:
> Hi,
>
> Sorry to bother you guys, but could anyone kindly offer me a spec2000
> alpha binaries? The download link in SS website is 404 now.
while, but, I
finally got around to creating the wiki page. In it, I describe my
methodology for managing change in my local repo, i.e., by using mercurial
queues. I believe most of the gem5 devs make heavy use of MQs as well.
http://gem5.org/Managing_Change_in_Your_Local_Repository
Anthony Gutierrez
It is possible with the classic memory system. I don't know much about Ruby
but, from that assert it appears as though it's not possible in Ruby.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, Mar 12, 2013 at 10:04 AM, Maxime Chéramy
wrote:
> Hello,
>
> When
a/src/mem/cache/builder.cc
+++ b/src/mem/cache/builder.cc
@@ -88,11 +88,7 @@
{
int numSets = size / (assoc * block_size);
-if (numSets == 1) {
-BUILD_FALRU_CACHE;
-} else {
-BUILD_LRU_CACHE;
-}
+BUILD_LRU_CACHE;
return NULL;
}
Anthony Gutierrez
http://web
That is a little tricky. An easy way to do this is to retain them on the
image by disabling the CoW layer. Although you need to be careful with this
and probably use separate images for each file you need generated.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Mon, Apr 15, 2013 at
I recommend using the latest development repository. The CPUs are
switching, but if you want to switch between atomic and O3 CPUs you need to
modify the CPU type of the repeat switch CPUs in Simulation.py.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Mon, May 13, 2013 at 10:51 PM
gem5 implements pseudo-ops. See src/sim/pseudo_inst.hh/cc
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, May 14, 2013 at 7:57 PM, Mahshid Sedghi wrote:
> Hello,
>
> I was wondering if gem5 implements magic instructions. I need to
> distinguish between the two
s = floorLog2(size) - 17; will yield a negative number.
Then, it tries to allocate a huge amount of memory, i.e., new FALRUBlk
*[numCaches];
See the ctor in fa_lru.cc
To override FA LRU tags see:
http://qa.gem5.org/42/how-to-set-a-fully-associative-l1-cache
Anthony Gutierrez
http://web.e
available anywhere?
Thanks
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
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you need to
set physical registers >= max number of arch registers + max number of
instructions in flight (ROB size).
Perhaps you're running into a similar issue with your rename changes.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Mon, Jul 15, 2013 at 1:56 PM, Xiangyang G
value on
commit.
Maybe someone who knows gem5's implementation can correct me on this.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Mon, Jul 15, 2013 at 2:40 PM, Korey Sewell wrote:
> Hi Tony,
> Are you saying that registers are *not* being freed upon commit?
>
> E
sizes
should be made much smaller.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Mon, Jul 15, 2013 at 2:43 PM, Xiangyang Guo wrote:
> Hi, I make the InstQueue size to 1 to make sure inorder issue, but I did
> not make any change to ROB because I think ROB doesn't harm
Here are the contents of the rcS for Replica Island I wrote:
#!/bin/sh
#Author: Anthony Gutierrez
sleep 10
/sbin/m5 dumpstats
/sbin/m5 resetstats
am start -n com.replica.replicaisland/.AndouKun
/sbin/m5 exit
I haven't tested it in a few years so I don't know if it still works, I&
but it was several years ago and I was
just trying to get some more apps to work on gem5.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Sun, Aug 11, 2013 at 6:14 PM, Xiangyang Guo wrote:
> Anthony,
>
> Thank you so much.
>
>
> On Sun, Aug 11, 2013 at 6:09 PM, Anthon
That is the inverse of the BW, i.e., the time in picoseconds.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Thu, Aug 22, 2013 at 5:32 PM, Lu Bai wrote:
> Hi all,
>
> I'm trying to change the bandwidth of SimpleMemory, the default value is
> 12.8GB/s and the simula
scripts to switch to a detailed CPU and enter back into simulation.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Wed, Aug 28, 2013 at 9:36 AM, יואב אורן wrote:
> Hi,
>
> I'm running Parsec benchmark with 1 or 4 CPUs with the Disk image from
> http://www.cs.utexas.edu
there actually be
something separate called Debug_Enable_Pri? If this is ok, I can submit
this patch.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
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I like to use the Linaro toolchain:
http://www.linaro.org/downloads/
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Wed, Jan 15, 2014 at 3:35 PM, Yu Wang wrote:
> Hi,
>
> I have some issues with the ARM cross compiling tools. Specifically,I am
> trying to install J
e behavior describing could be
reasonable.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Thu, Jan 16, 2014 at 9:01 PM, Milad Mohammadi wrote:
> Hi,
>
> The gem5 local branch predictor exhibits a larger number of mispredictions
> as you increase the size of the predictor.
r
increases aliasing probability drops and he number of mispredictions ought
to drop (unless a corner case happens)
On Thursday, January 16, 2014, Anthony Gutierrez wrote:
> I'm not quite sure exactly what it is you're doing, but if I am following
> correctly it doesn't seem like
What exactly are you setting to 32, 256, 1024, etc.? The local, global, or
choice predictor? Or all 3?
You can try getting a trace of the branches by using gem5.opt
--debug-flags=Fetch. That way you can see if the predictions are behaving
as expected.
Anthony Gutierrez
http://web.eecs.umich.edu
Here would be good: http://gem5.org/BBench-gem5
Have you confirmed this patch works with the latest version of gem5? I
think some m5ops have been added/modified.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, Feb 11, 2014 at 12:47 PM, Martin Brown wrote:
> Sure I can do t
Are you using the python scripts that are provided on that page?
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Tue, Feb 25, 2014 at 2:04 PM, Aditya Deshpande <
adityamdeshpa...@gmail.com> wrote:
> Hi,
>
> I am following the information provided in the gem5 we
data.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Sat, Mar 8, 2014 at 9:23 AM, senni sophiane wrote:
> Hi everybody,
>
> In stats file, I can find "dcache.WriteReq_accesses" corresponding to the
> number of write request accesses in D-Cache. However, there is no
There is an updated readme in that tarball that contains detailed
instructions for how everything in the tarball was built.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Wed, Apr 9, 2014 at 1:40 PM, Neal Haas wrote:
> Hi all,
>
> I'm trying to understand how the v
The latest version of the README has all the steps necessary to build the
kernel, image, and dtb files.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
On Wed, Apr 9, 2014 at 2:01 PM, Neal Haas wrote:
> Thanks for the fast response Anthony.
>
> I have followed these instruc
,
Anthony Gutierrez
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Hello All,
I am trying to more accurately model the memory system for the ARM ISA
(running Android) as well as implement some of the ARM cache flushing
instructions. One problem i'm running into is that the icache contains
dirty data. Looking at the code in cache_impl.hh I see that when a read
req
How are you running gem5? I.e., what is the command line you used?
-Tony
On Sun, Nov 20, 2011 at 12:14 AM, yanke wrote:
> It stops there nearly 5 hour. I don't know how long it will continue to be
> there.
>
>
>
> At 2011-11-20 00:17:27,"Ali Saidi" wrote:
>
> It's probably still booting, it ta
The simple CPUs, atomic and timing, execute a single instruction in its
entirety each cycle. Thus, they do not require branch prediction.
-Tony
On Sun, Nov 20, 2011 at 7:59 AM, Mahmood Naderan wrote:
> hi,
> how branch instructions are predicted in a TimingSimpleCPU? As I
> searched the code, th
>
> At 2011-11-20 22:14:28,"Anthony Gutierrez" wrote:
>
> How are you running gem5? I.e., what is the command line you used?
>
> -Tony
>
> On Sun, Nov 20, 2011 at 12:14 AM, yanke wrote:
>
>> It stops there nearly 5 hour. I don't know how long it wi
It seems as though a recent changeset has broken things. I have tried
running the full-system linux files from gem5.org as a sanity check and I
get the same error even with those. So, it's not an issue specific to the
BBench kernel/disk image.
-Tony
On Wed, Dec 14, 2011 at 4:15 PM, Rio Xiangyu Do
** **
>
> This issue is fixed now. The reason it wasn't caught before is people
> normally use caches in timing mode and gem5 requires caches with the o3 cpu.
>
>
> ** **
>
> Ali
>
> ** **
>
> On Dec 14, 2011, at 6:45 PM, Anthony Gutierrez wrote:
When I run ./build/ARM_FS/gem5.opt
> ./configs/examples/fs.py -b ArmAndroid, I can't boot into vnc. When I run
> ./build/ARM_FS/gem5.opt ./configs/examples/fs.py -b bbench, it says there
> is no bbench. I use the developing repo.
>
>
>
> At 2011-11-21 10:17:31,"Antho
ouse.nolock.clean.img)
> @ cycle 0
> [open:build/ARM_FS/dev/disk_image.cc, line 79]
> Memory Usage: 412200 KBytes
> Program aborted at cycle 0
> Aborted (core dumped)
>
>
>
>
> At 2011-12-16 00:47:11,"Anthony Gutierrez" wrote:
>
> You need to add
t
> xiao
>
>
>
> On Dec 18, 2011, at 9:19 AM, yanke wrote:
>
> I tried BBench, it has the same problem.
>
>
> At 2011-12-16 22:43:29,"Anthony Gutierrez" wrote:
>
> That is because you are trying to run ArmAndroid, not BBench. Your command
> line shoul
Could not load kernel file
>
> I have no problem when I'm booting the android system, I use the kernel
> and disk image on http://gem5.org/Bbench-gem5
>
> I'm not sure whether this is the correct way to run rcS or do I need to
> modify path?
>
> Thanks!
>
>
.img)
>
> @ cycle 0
> [open:build/ARM_FS/dev/disk_image.cc, line 79]
> Memory Usage: 412204 KBytes
>
> Program aborted at cycle 0
> Aborted (core dumped)
>
>
>
> At 2011-12-20 00:31:06,"Anthony Gutierrez" wrote:
>
> That is because you are using
Sounds like you have the right idea if you are getting a vnc output. Also,
the framebuffer will show you if it's booting/running properly. If the
bbench exited correctly the simulator output will say say that it stopped
because the m5 exit instruction was encountered. Also, the framebuffer will
dis
t; How do I resolve this?
>
> Regards,
> Kirtika
>
>
>
>
>
> On Fri, Jan 20, 2012 at 9:24 PM, Anthony Gutierrez wrote:
>
>> Sounds like you have the right idea if you are getting a vnc output.
>> Also, the framebuffer will show you if it's boot
BBench works fine out of the box with the current repo. The patch causing
the problem which led me to suggest you use revision 7f762428a9f5 has been
fixed in the current repo. And as I said, that was only a temporary
solution anyhow.
You are using the wrong kernel. You are using the kernel that co
nd as for gem5.opt, it fails at
> link stage due to vague c++ undefined reference issues.
>
> Regards,
> Kirtika
>
>
> On Sat, Jan 21, 2012 at 10:08 PM, Anthony Gutierrez wrote:
>
>> I just noticed this too. I haven't looked too in depth into it so I don't
In this case (a 512 B cache, 64 B line, 8 way) you have a fully associative
cache. I think the FA_LRU tags don't work properly. You need to change
things to never use the FA_LRU cache, see if that helps.
On Wed, Feb 8, 2012 at 1:45 PM, Mahmood Naderan wrote:
> block size is 64 and assoc is 8
>
>
, Feb 9, 2012 at 2:17 AM, Mahmood Naderan wrote:
> but the error points to lru.cc:58
>
> if (numSets <= 0 || !isPowerOf2(numSets)) {
>fatal("# of sets must be non-zero and a power of 2");
> }
>
> i doubt if it is related to fa_lru
>
>
> On 2/9/12, An
lru is used.
> http://www.mail-archive.com/gem5-users@gem5.org/msg01511.html
>
> While debugging at this line (lru.cc:58), I noticed that the problem
> is not "power of 2". Instead number of sets are zero:
>
> if (numSets <= 0 || !isPowerOf2(numSets)) {
>fat
Are the kernels on gem5.org (specifically the ARM kernel) compiled with
this?
Thanks,
Tony
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First thing you should do when you get errors like this is check the repo.
This issue was fixed last week.
On Feb 17, 2012 9:02 AM, "Mahmood Naderan" wrote:
> Hi,
> What happened to this line:
>
> system.l2.num_cpus = options.num_cpus
>
> seem sthat BaseCache.py has no longer "num_cpus" field. So
I don't think the mercurial repo is up since kernel.org was hacked. You
should still be able to checkout the source using git though.
On Mon, Feb 20, 2012 at 10:30 PM, Ali Saidi wrote:
> Cloning the following should work:
> http://www.kernel.org/hg/linux-2.6/
>
> Ali
>
> On Feb 20, 2012, at 7:45
Hello,
I tried adding packages to the Ubuntu image from gem5.org. I followed the
instructions from the link below to try to add packages to this image,
however, apt-get just hangs when trying to add packages because it can't
connect to the repo.
When I build my own image using the method describe
s. I'm having no trouble mounting
> the disk image on the website and running apt-get either. Not sure
> what the problem could be at this point. What version of Ubuntu are
> you using rootstock with? How are you creating the disk image?
>
> Geoff
>
> On Fri, Mar 2, 20
ll.
3) The one on gem5.org does not have a mounted-tmp.conf script.
4) The one on gem5.org does not have the line swapon /swapfile # if
present, as indicated in the instructions.
On Fri, Mar 2, 2012 at 3:19 PM, Anthony Gutierrez wrote:
> I was originally using the default (ext2), but I not
I believe this does have something to do with the permissions, and, I'd say
the init.rc script is where you should do this anyhow.
On Sun, Mar 4, 2012 at 2:39 PM, Kirtika Ruchandani wrote:
> Hi,
> @Gabe: Thanks - that gives me some clarity. You are probably right about
> Android being unhappy abo
You need to add the header to the file in which it is being used. E.g.,
foo.hh. It will be generated.
On Wed, Mar 14, 2012 at 2:19 PM, Paul Rosenfeld wrote:
> Hello all,
>
> I'm making some changes in M5 and I was hoping to add my own DPRINTF flag
> to track them through the simulator. I saw that
ed. Thank you.
>
> On Wed, Mar 14, 2012 at 2:23 PM, Anthony Gutierrez wrote:
>
>> You need to add the header to the file in which it is being used. E.g.,
>> foo.hh. It will be generated.
>>
>> On Wed, Mar 14, 2012 at 2:19 PM, Paul Rosenfeld wrote:
>>
>>&g
I would suggest taking a checkpoint after the system boots and before
bbench launches. This can be inserted in the bbench.rcS script by adding
/sbin/m5 checkpoint right before bbench is launched. Then you can restore
into O3. This should shave about a day off of simulation time since, im my
experie
ut from what I understand there is no way to reduce the 12
> hours time to anything lesser, because it's already running the
> fastest CPU type (in terms of simulation speed).
>
> Anirudh
>
> On Wed, Mar 21, 2012 at 12:42 PM, Anthony Gutierrez
> wrote:
> > I woul
Hello All,
Have the fully associative tags (FA_LRU) ever worked? I know I can use LRU
and just set the associativity accordingly, but, FA_LRU are supposed to be
faster in terms simulation time, correct?
I get a segfault in the first call of handleFill() around line 1127:
if (pkt->isRead()) {
Hello,
I am working with some code that relies on the correct implementation of
the ARM CCSIDR (
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/CIHGGJAB.html)
control
register see: src/arch/arm/isa.cc:readMiscReg(). I'm trying to implement
this (and the CSSELR
http://infocent
Is the value used for the ARM MISCREG_CTR register (see /arch/arm/isa.cc
~line 221), which is 0x86468006, correct? It seems as though it is
incorrect, for the I-Min and D-Min fields at the very least. Accodring to
the A15 TRM these values should be log2(#words of minimum cache line of all
caches th
Oh, sorry. That is an artifact of the way the system used to be built. Now,
the binaries for FS/SE are combined into a single binary. So to run you
would do something like the follow:
./path_to_gem5_root/build/ARM/m5.fast configs/example/fs.py -b bbench
--kernel=/path_to_gem5_system/binaries/vmlin
1) Correct
2) I believe the default is 2 seconds on the version for gem5. You can
always mount the image and browse/modify the bbench source.
3) By default the system runs with 1 cpu. -n 1 and not specifying -n are
the same.
4) No. You can modify the branch predictor by changing the params in
O3
Did you run in atomic mode? Also, is that the host_seconds from the first
stats dump, or the second?
-Tony
On Wed, Apr 4, 2012 at 10:38 AM, Tony Feng wrote:
> Hi,
>
> After I ran BBench, I found in the stats that host_seconds is 3443.57. I
> didn't time the whole simulation, but at least I know
ime of the
benchmark. Can anyone with more knowledge of the stats confirm this?
-Tony
On Wed, Apr 4, 2012 at 10:49 AM, Tony wrote:
> Anthony Gutierrez umich.edu> writes:
>
> >
> >
> > Did you run in atomic mode? Also, is that the host_seconds from the first
> stats dum
The instructions at http://gem5.org/BBench-gem5 assumes the reader already
has some familiarity with gem5. In gem5 there are options for running
certain portions of a benchmark using the fast atomic mode, then running
the region of interest using the detailed mode. Search the wiki and/or
mailing li
That's correct you don't have to worry about cache maintenance. No, the
d-cache is not write-through. It doesn't need to be.
I have some patches for the i-cache maintenance operations (mcr icimvau,
icialluis) and the d-cache wouldn't be difficult to implement using these
as a base. They implement
Did you have the python dev library installed?
-Tony
On Tue, Apr 24, 2012 at 5:55 PM, Thomas, Amanda J <
amanda_tho...@student.uml.edu> wrote:
> Hi,
>
> I'm having trouble running bbench. I followed the instructions on
> http://m5sim.org/BBench-gem5 and have everything installed. I exported
>
Sorry, I mean, do you have the python header files installed?
-Tony
On Tue, Apr 24, 2012 at 9:16 PM, Anthony Gutierrez wrote:
> Did you have the python dev library installed?
>
> -Tony
>
>
> On Tue, Apr 24, 2012 at 5:55 PM, Thomas, Amanda J <
> amanda_tho...@student
There is still some problem with your path. Are you sure M5_PATH is set
correctly? What is the output of echo $M5_PATH? If you are sure that is
correct try adding the absolute path to the SysPaths.py, line 53.
-Tony
On Sat, Apr 28, 2012 at 11:09 AM, Thomas, Amanda J <
amanda_tho...@student.uml.ed
That is strange. This means that it's likely not defined in your
Benchmarks.py file. Which version of gem5 are you using?
-Tony
On May 2, 2012 1:35 PM, "James Stadtmiller" <
james_stadtmil...@student.uml.edu> wrote:
> So, after fixing my gcc build to use 4.5.3, I was able to successfully
> compil
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