Is the value used for the ARM MISCREG_CTR register (see /arch/arm/isa.cc ~line 221), which is 0x86468006, correct? It seems as though it is incorrect, for the I-Min and D-Min fields at the very least. Accodring to the A15 TRM these values should be log2(#words of minimum cache line of all caches the processor controls). The values for both fields ix 0x6, which leads me to believe that this was encoded as log2(#bytes...), which may have just been a small error.
Let me know if I am misinterpreting something, or if I am correct. If so, I'll submit my patch. -- Thanks, Tony
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