>
> I am not sure how to rectify the error still though..
>
> Pritha
>
>
> On Sat, Feb 18, 2012 at 5:47 PM, Ali Saidi wrote:
> If you get an execution trace right before this happens that might shed some
> light on it. Tracking how the address that is being used is as
> generated. This value gets stored in address A=0xfc000722b930.
>
> I am still confused about how you don't see this error, do I have some old
> versions of files?
>
> Pritha
>
> On Mon, Feb 20, 2012 at 10:34 AM, Ali Saidi wrote:
> I wonder who wrote to
Cloning the following should work:
http://www.kernel.org/hg/linux-2.6/
Ali
On Feb 20, 2012, at 7:45 PM, Pritha Ghoshal wrote:
> Hi Sudhanshu,
>
> I am trying to compile a linux kernel as well, but I am not able to get the
> first step runnning, the hg clone of the linux-kernel repo. Were you
ownload the kernel from the ftp repository?
>
> Pritha
>
> On Mon, Feb 20, 2012 at 6:40 PM, Ali Saidi wrote:
> Hi Pritha,
>
> I really don't know. The kernel I tried was 2.6.27.6 and is a the mercurial
> repository of the linux kernel with the following patch qu
It issues a prefetch if the address it's trying to prefetch doesn't exist in
the mshr or write queue. You generally don't want to prefetch something that
you're currently waiting for. That is wasted bandwidth.
Ali
Sent from my ARM powered device
On Feb 21, 2012, at 1:49 AM, Mahmood Naderan
Hi Seyed,
The number is currently limited by the generic interrupt controller we have
modeled. In theory it supports 8 CPUs, although I've never tried more than
four and you might need to do some hacking in Linux to get it to see that there
are more that four available in the platforms we sim
Hi Heba,
I think you've run into a corner case with some changes
we just made to the repository.
Could you try putting a line like the
following in cache_impl.hh:996 (right above tags->invalidateBlk(blk);):
blk->status &= ~BlkValid;
Thanks,
Ali
On 21.02.2012 16:10, Heba
Saadeldeen wr
; I'll try that out, should I make a new repo under the repo.gem5.org?
>
> Pritha
>
> On Mon, Feb 20, 2012 at 9:33 PM, Ali Saidi wrote:
> It seems like it's broken at the time. Yes you could start with a the kernel
> source tar ball.
> http://www.kernel.org/pub/l
Hi Xuhao,
The module warnings aren't problems, the kernel is trying to load a module to
help it deal with the file you're provided, the issue is the binary you
compiled. Are you sure that you successfully cross compiled it? Normally errors
like the one below happen when you try to run a binary
Hi Trang,
Could you run gem5 in a debugger and get a back trace.
We need a bit more information to debug it.
Thanks,
Ali
On
22.02.2012 02:43, Trang Le wrote:
> Hi,
>
> I was trying to run
PARSEC benchmarks in X86 FS mode with Ruby (my gem5 was updated
recently). However, I've run into
ontinue (try -v)
> patch failed, rejects left in working dir
> errors
during apply, please fix and refresh stable/patch_to_2.6.27.6.diff
> I
had to use
> hg qpush -a -v to actually apply the patches..
> Pritha
>
> On Tue, Feb 21, 2012 at 8:43 PM, Ali Saidi
wrote:
>
hat Full-system only supports a single
thread for the moment. But I don't understand how are you going to run
multiple threads then? Can't we allow multiple threads to run at the
same time?
>
> Thanks,
> Heba
>
> On Tue, Feb 21, 2012 at 3:18 PM, Ali
Saidi wrote:
>
&g
Unless you provide exact command lines and output there is no way
anyone wil be able to replicate your problem.
Ali
On 22.02.2012
13:53, Ankita (Garg) Goel wrote:
> I have been facing the same issue
with the new version and am unable to figure out what is causing it. I
am unable to do swit
Hi Pritha,
It looks like you're correct for (1) at first glance.
With regards to (2) it seems as though v2.5 of the manual said cache
line == 1, descriptor == 0; while the latest version reversed that. It's
listed as a change in the manual, so it was probably a misprint.
Finally, with regards
On 28.02.2012 11:27, Gedare Bloom wrote:
> On Tue, Feb 28, 2012 at
11:15 AM, Xuhao Chen wrote:
>
>> Hi Gedare, I have
read your blog "a week in m5". And I have a question about m5. The
Solaris 10 binary image for SPARC includes "reset.bin, q.bin,
openboot.bin" etc. I copy *.bin and nvram1 fr
student
>
>
School of Computer
>
> National University of Defense Technology
>
>
Changsha, Hunan, P.R.China, 410073
>
> Tel: +86-159-741-03340 (Mobile)
>
> FROM: Ali Saidi [1]
> DATE: 2012-02-29 07:20
> TO: gem5 users
mailing list [2]
> SUBJECT:
Hi Samuel,
You can include a ram disk by taking part of the
physical memory and placing a ram disk there. For example for a ram disk
in linux (provided you had a ram disk driver is the kernel), you could
add something like:
self.ramdisk = PhysicalMemory(range =
AddrRange(Addr('128MB'), size
rough the implementation files to get all the possible
settings I can make in the config script?
> Best,
> Samuel
>
> On
Wed, Feb 29, 2012 at 5:35 PM, Ali Saidi wrote:
>
>> Hi Samuel,
>>
>> You can include a ram disk by taking part of the
physical memory an
the ATAG_INITRD2 and ATAG_RAMDISK tags
accordingly? Does it set the ATAG_* tags at all?
> Best,
> Samuel
>
>
On Wed, Feb 29, 2012 at 6:27 PM, Samuel Hitz
wrote:
>
>> Hi Ali,
>> Thanks for the clarification, this should get
me started.
>> Best,
>> Samuel
>>
Hi Andrew,
The first guess is that possibly the cpu results in a
different code path or different scheduler decisions which lengthen
execution. Another possibility is that the O3 cpu as configured by the
arm-detailed configuration has some issue. While this is possible it's
not incredibly like
648951747
> Thanks,
> Andrew
>
> On Thu, Mar
1, 2012 at 2:40 PM, Ali Saidi wrote:
>
>> Hi
Andrew,
>>
>> The first guess is that possibly the cpu results in a
different code path or different scheduler decisions which lengthen
execution. Another possibility
Assuming you haven't specified a checkpoint directory, they're
placed in the output directory which is by default m5out. Each
checkpoint is a directory named cpt.XXX where X is the
simulator tick in which the checkpoint was created.
Ali
On
01.03.2012 17:52, Amber Sami Kubesch
How does x86 implement locked transactions? Are they done via load locked/store
conditionals?
Ali
Sent from my ARM powered mobile device
On Mar 2, 2012, at 10:53 PM, Gabe Black wrote:
> I dug into this some more, and it looks like it really is because the memory
> system doesn't enforce loc
is because they don't have checker's setup in the code. Let
> > me know if otherwise.
> >
> > Thanks,
> > Andrew
> >
> >
> > On Thu, Mar 1, 2012 at 5:00 PM, Ali Saidi wrote:
> >>
> >> Hi Andrew,
> >>
> >>
> >>
>
a checkpoint.
>
>I'll work on getting you results from another benchmark. In the meantime,
> let me know if you have any other ideas.
>
> Thanks,
> Andrew
>
> On Sat, Mar 3, 2012 at 2:14 PM, Ali Saidi wrote:
> Hi Andrew,
>
> Are you sure the benchmar
> Thanks,
> Andrew
>
> On Sat, Mar 3, 2012 at 3:12 PM, Ali Saidi wrote:
> Hi Andrew,
>
> You could get a trace using debug flag Exec and seeing where the extra
> instructions are coming from. You might want to sleep for 10 or 15 seconds
> before running your benchmark and
> Link [7]
> Best,
> Samuel
>
> On Thu,
Mar 1, 2012 at 4:43 PM, Ali Saidi wrote:
>
>> Hi
Samuel,
>>
>> We do setup atags, but not the initrd and ramdisk
although in theory those could be added.
>>
>> See
src/arch/arm/linux/atags.hh and s
tiate the
PhysicalMemory correctly together with the ramdisk.
>>> Here is my
system script if you want to take a look at it:
>>> Link [7]
>>> Best,
>>> Samuel
>>>
>>> On Thu, Mar 1, 2012 at 4:43 PM, Ali Saidi
wrote:
>>>
>>&g
You can check if the request hasContextId() and then use contextId()
to get the context Id which nominally is the core. You could also get
the masterId and match it to the system.cpuX string it registered with
depending on exactly what you're looking for.
Master IDs are assigned
to every reque
The wiki page has been updated.
Ali
On 08.03.2012 10:21, Samuel
Hitz wrote:
> Hi,
> I'm trying to remote debug an ARM kernel on gem5.
However as soon as I attach the remote debugger I get:
>
> (gdb)
target remote localhost:7000
> Remote debugging using localhost:7000
>
Remote 'g' pack
I imagine that your jumping to a i/o device or a bad-address
responder in the memory system and trying to access it with a cache
block sized request. You should be able to figure out what's gone wrong
with some trace flags, but if you want to get gdb attached at cycle 0
just set rgdb_wait in sim
Parse the name() which has cpu0 in it?
Ali
On Mar 11, 2012, at 12:10 PM, 陳冠廷 Eric K.-T. Chen wrote:
> Hi,
>
> I know that it is able to fetch a CPU id inside a packet, as previously
> discussed in the thread "Regarding CPU id". But if I don't want to do the
> transaction (i.e. without transfe
Hi Samuel,
It's because of virtual vs physical addresses. When the kernel starts it is
operating on physical addresses and all the symbols were read in have virtual
addresses. You could hack the code to set a breakpoint on a physical address or
just set break points by address instead of symbol
On 12.03.2012 21:18, Tony Feng wrote:
> Hi,
> The plan is to make
ARM FS simulation work with Ruby. Btw, has anyone done this work so far?
I'm new to GEM5, so not very familiar with the code structure yet.
> As
a start, I made some changes on ruby_fs.py, and added a new class into
FSConfig.p
The error is that there are more that 1500 instructions currently in
flight in the system. It could mean several things:
1. The value is
somewhat arbitrarily defined and maybe there are more than 1500 in your
system at one time?
2. Instructions aren't being destroyed correctly
You could tr
You have a null pointer.
Ali
On 14.03.2012 05:23, Iordan
Alexandru wrote:
> #3 FunctionProfile::dump (this=0x0, tc=0x94d8208,
os=...) at build/ALPHA_FS/cpu/profile.cc:126
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Hi Nathanaël,
It appears as though that is the case. Have you
tried switching them and observed changes/issues?
Thanks,
Ali
On
14.03.2012 06:48, Nathanaël Prémillieu wrote:
> Hi everyone,
> I'm
currently looking at the *.isa file to see how the decoder is
generated.
> In the file arch/
On 15.03.2012 11:10, Tony wrote:
> Hi Digant,
>
> Thanks for
offering your work. I need to use ruby for its topology setup. Since
>
you said the test was without ruby, do you think your DMA model is
compatible
> with ruby? If so, I would very much like to have a
try.
You dont need this pro
Hi Dave,
In theory it is, but I don't know if anyone has tried it in a long time. I'd
suggest taking a checkpoint and restoring into a different cpu model.
Thanks,
Ali
On Mar 16, 2012, at 4:18 PM, David Roberts wrote:
> Hey,
>
> Is switching CPUs inside Linux still supported? The /sbin/m5 sw
This is a problem with your compiler not returning the correct thing or not
being in your path.
If you need to you can specify the compile on the command line by setting CC=
and CXX= but nominally, they should be found if it's a standard compiler (e.g.
gcc) and in a normal location (e.g. /usr/b
What do you want to change?
You can change the directory that it's output to. system.terminal is just the
output of the serial console from the system.
Ali
On Mar 6, 2012, at 11:28 PM, Heba Saadeldeen wrote:
> Hi,
>
> I am running parsec benchmarks and I am trying to make sure the benchmark
Hi Anirudh,
By default gem5 uses the AtomicSimpleCPU. If you would
like to get timing information you'll probably need to use the
out-of-order CPU model which will take longer to run. It's an open
question how to best sample with a multi-threaded browser type workload.
It would be great to kno
Steve,
M5_OVERRIDE_PY_SOURCE is what you're looking for, setting
it to TRUE will do the trick.
Ali
On 24.03.2012 23:02, Steve
Reinhardt wrote:
> The .py files that are outside configs are compiled
into the gem5 binary, so if you change any of them you have to re-run
scons to see the effe
Hi Samuel,
The idea is that if you experience this you'd want to
know about it, so we issue a SIG_TRAP which causes a debugger to stop
execution so you can examine what is wrong. I highly recommend that you
create a new barrelfish system (e.g. src/arm/arm/barrelfish/system.*)
and do the right
Take a look at:
http://mercurial.selenic.com/wiki/EditingHistory
Ali
On 26.03.2012 15:59, Paul Rosenfeld wrote:
> I'm sorry this
isn't directly a GEM5 question, but my google fu is failing me.
> I
have my gem5 repo that I've been working on and making commits directly
to my local reposi
Hi Anirudh,
src/dev/ethertap.* might be what you're looking for,
but I don't know that the code has been used in quite some time. Also,
because you'll be interfacing with the real world, the simulation will
not be deterministic.
Ali
On 26.03.2012 19:02, Anirudh Sivaraman
wrote:
> On Mon,
Another question is does /var/log/syslog provide anything useful?
Ali
On 27.03.2012 12:01, Mahmood Naderan wrote:
> do you have
enough memory?
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If you change the values in the py files in the source tree you need
to re-compile the binary.
You can go to all the bridges and in the
config files and change their sizes:
something like:
system.iobridge.req_size_a = 64
Ali
On 28.03.2012 00:12, Teng Lu
wrote:
> Hi All,
>
> I've als
Original Message
SUBJECT:
Re: [gem5-dev]
Review Request: MEM: Remove legacy DRAM in preparation for memory
updates
DATE:
27.03.2012 08:31
FROM:
"Andreas Hansson"
A quick test shows that we do still print the error message
fatal:
Object file is a dynamic executable however only static executables are
supported!
Please recompile your executable as a static binary and try
again.
when someone tries to run a dynamically linked binary.
Ali
On
28.03.2012
Does it terminate with an error code?
Seems like it should be
printing some more output.
Ali
On 28.03.2012 22:21, Anirudh
Sivaraman wrote:
> On Wed, Mar 28, 2012 at 3:53 PM, Pritha Ghoshal
wrote:
>
>> Hi Anirudh, Have you tried checking
the m5out directory? The stats.txt file is genera
You should look at the executed output and see where the address
0x11 is coming from. Also, I'm not sure why you're using the gem5
m5a_getid(). Do you know what it does?
Ali
On 29.03.2012 04:47,
Mohamed hédi Ghaddab wrote:
> Sorry, I put the wrong command line. in
fact, my program is stati
It would be nice, but I don't know of necessarily a better way to do
this. One possibility is adding pointers to the system object that can
be manually setup with the appropriate caches.
For example
system.l1d = system.l1dcache.
Then the ARM system will have the
pointers directly which sho
Following the instructions in that email works fine. I'm not sure
why you've had an issue as it's configured exactly as every other object
is in gem5.
--- a/configs/example/se.py Wed Mar 28 11:10:50 2012
-0500
+++ b/configs/example/se.py Thu Mar 29 03:49:06 2012 -0500
@@
-204,6 +203,7 @@
syst
You probably don't want to do that as the simulation will no longer
be deterministic. If you really do want to you can set the rtc object's
time parameter = 'Now'.
Ali
On 29.03.2012 09:23, Jinchun Kim wrote:
> When we start gem5 simulation, we face this real-time clock set
message.
>
> w
Hi Tony,
It very likely could be wrong. In most users cases it doesn't matter, but if
you're trying to handle cache maintenance requests that could be problematic.
Ali
On Mar 30, 2012, at 5:23 PM, Anthony Gutierrez wrote:
> Is the value used for the ARM MISCREG_CTR register (see /arch/arm/isa
Hi Tao,
There are some issues with switching the O3 CPU in and out and it needs some
debugging. There are some patches on the review board which may solve your
issue.
http://reviews.gem5.org/r/1092/
Ali
On Mar 30, 2012, at 4:47 PM, Tao Zhang wrote:
> Dear all,
>
> Sorry to bother if this is
Threads in this context are threads executing on a cpu. By default all cpus
only have a single thread (e.g. they are NOT SMT).
Ali
On Mar 30, 2012, at 8:54 AM, Hamid Reza Khaleghzadeh wrote:
> I have executed a multi-threaded application on Gem5 by Exec debug
> flag. In the obtained trace file,
ThreadId is the hardware thread executing on a single CPU. ContextId is the
execution context (think register file + PC) for a given cpu.
Getting the process id and sw thread id isn't particularly easy, although there
are some bits of code to help for some architectures. You need to examine the
Hi Zheng,
If you link your program with the m5 ops in util/m5 you
should be able to put
m5_dumpreset_stats(0,0);
__kernel();
m5_dumpreset_stats(0,0);
and that should accomplish what you want.
Ali
On 02.04.2012 09:39, Zheng Wang wrote:
> Hi,
> I wonder how I
can dump simulation s
Did any of them produce more output that you have listed below. You
should see some sort of error message.
Thanks,
Ali
On 03.04.2012
05:58, Iordan Alexandru wrote:
> Issuing just "scons" is equivalent to
"scons build/ALPHA/gem5.debug". But I tried:
> scons --verbose
build/ALPHA_MOESI_CM
s/ALPHA
> machine:~/gem5$
>
> Maybe is
worth mentioning that this is happening after I updated and merged to my
old repository. But even if the merger screw something up, I still
should get some kind of error message right? Since I have no errors, I
am blindly looking through SConstruct a
I think it probably should. Anyone else?
Ali
On 04.04.2012
12:28, Paul Rosenfeld wrote:
> http://www.m5sim.org/Debugging [1]
>
http://www.m5sim.org/Debugging_M5 [2] I just noticed that there are two
pages about debugging M5 and they seem to have some content overlap but
it looks like "Deb
Could you create a patch that fixes the problem and put it on the review board?
reviews.gem5.org?
Thanks,
Ali
On Apr 8, 2012, at 7:31 PM, Tao Zhang wrote:
> Dear all,
>
> I found that the option "--maxtime (# of second in float)" didn't work once i
> tried to use it to terminate the simulati
You probably also need an import m5 line at the top as well.
Ali
On 11.04.2012 07:45, Mahmood Naderan wrote:
> the script in the
website is old. You have to do
> addToPath('../common')
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If you could give us the exact output, that would help.
You might
try deleting the build directory if it got corrupted in some way.
Thanks,
Ali
On 11.04.2012 09:57, Thomas, Amanda J wrote:
> Hi
>
I get an error when I'm trying to build gem5 with this command:
> scons
build/ARM/m5.fas
The only think that you could do is install a SIGABRT handler that
would close all the open files gracefully. I believe abort() closes all
open files, but there might be unencoded output in the gzstream object
that hasn't been flushed.
Ali
On 11.04.2012 13:19, Andrew Cebulski
wrote:
> Hi a
Should we update the minimum version of swig on the website to 1.3.40?
Ali
On Apr 19, 2012, at 9:48 AM, Thomas, Amanda J wrote:
> You're right, I wasn't installing the updated version of swig correctly. Now
> I have and gem5 builds!
> Thank you,
> Amanda
> From: gem5-users-boun...@gem5.org [ge
You need to compile an updated version of the console binary in the
gem5/system/alpha/console directory.
Ail
On Apr 18, 2012, at 4:56 PM, Seongil O wrote:
> Hi all,
>
> Could anyone inform me the way to configure more than 1GB physical memory on
> ALPHA_FS machine?
>
> The ALPHA_FS works quit
To be able to debug errors like this we need a reproducible example where it
fails and some trace output with debug flags like Cache, Bus, CacheRepl, etc.
Ali
On Apr 16, 2012, at 2:28 PM, Chao Chen wrote:
> Hi,
>
> I find that in cache_impl.hh, when a cache receives a read request, it
> would
Looks like a remote gdb session is causing a read request to a address that is
part of the GIC. The GIC expects all reads targeting it to original from a CPU
and thus have a context id.
Do you have a remote debugger attached? You could change the gig to ignore any
requests that don't have a co
Perhaps a port scanner connected to the open port?
Ali
On Apr 14, 2012, at 10:34 AM, Sathyanarayanan S wrote:
> Thanks Andreas,
> But I am new to gem5 simulator. Can you explain the procedure in detail?
>
> On Fri, Apr 13, 2012 at 1:47 PM, wrote:
> Send gem5-users mailing list submissions to
This bug should be fixed by now.
Ali
On Apr 14, 2012, at 3:47 PM, mingkai huang wrote:
> I tried the gem5-stable-549b72de8f72, and got:
>
> panic: Pio port of system_cpus_interrupts not connected to anything!
>
> When using gem5-d062cc7a8bdf, I got:
>
> Segmentation fault (core dumped)
>
> I
The difference is likely the snoops bouncing back from the memory bus to
enforce coherence in the caches. The L2 doesn't know if it's the only cache in
the system or if there are multiple, so it always snoops, even in the
uniprocessor case.
Ali
On Apr 9, 2012, at 5:06 AM, Haishan Zhu wrote:
>
Look for PrintThreadInfo in the code, but you'll need to remove a false
constant in src/alpha/linux/system.cc to make it work.
Ali
On Apr 19, 2012, at 2:00 AM, Sudhanshu Jha wrote:
> Hello,
>
> Can you please suggest as to how can i distinguish between the processor tid
> and a benchmark tid
They're not glued to files, but objects. The type field in the Python objects
connects them to C++ objects.
Ali
On Apr 21, 2012, at 3:52 AM, Anirudh Sivaraman wrote:
> I am posting this to both the user and the dev list since I don't know
> where this falls.
>
> I read here (http://www.m5sim
Looking at the the output below it looks like somehow the cf device
is getting a -1 because of the panic. Perhaps you didn't download the
entire disk image, can't read the disk, etc?
Ali
On 23.04.2012
05:44, mihai pricopi wrote:
> Hi,
>
> I am new to gem5. I've been
trying to run a FS wit
Hi Samuel,
The invalidations aren't needed for correctness, gem5
supports i cache snooping of invalidates and that is a perfectly
acceptable thing to do from an architecture perspective. If you want to
implement cache flushing/invalidation you'll first need to add the
ability to do that to the
; Makes sense to me.
We should also remove the "do not use >2 and above" statement as that
works absolutely fine these days.
>>
>> Andreas
>>
>> FROM:
gem5-users-boun...@gem5.org [4] [mailto:gem5-users-boun...@gem5.org [5]]
ON BEHALF OF Ali Saidi
>> SENT
problem.
> Do
you have any idea what went wrong?
> Thanks, again!! Kiyeon
>
> On
Sun, Apr 22, 2012 at 7:36 AM, Ali Saidi wrote:
>
>> The VExpress_ELT platform probably isn't useful for you, but the
VExpress_EMM one should be and will likely be supported in the f
At the time that loadState is called we need to be able to do a functional
access. That is the issue here.
Ali
On Apr 25, 2012, at 5:52 PM, Nilay Vaish wrote:
> Ali, this problem is related to patch 8885 that you committed last month. Can
> you figure out why functional accesses are made bef
Looking at util/m5/m5op_arm.S should give you a petty good idea.
Ali
On 26.04.2012 15:13, Amin Farmahini wrote:
> Hi,
>
> I am
trying to add a couple of pseudo instructions to ARM ISA. I used the
reserved opcodes (0x56 to 0x59) in util/m5/m5ops.h . I could not find
any examples for binary
Hi Mark,
You could return in the system call but schedule an event
that quiesced the CPU in question until a the condition was satisfied.
Thanks,
Ali
On 27.04.2012 16:23, Mark Browning wrote:
> Howdy
all,
> I'm adding custom system calls to provide inter-processor
communication in a s
The error message is printed with hex and the flags are listed with octal, so
they're not the same. It's complaining about NOATIME which as it turns out is
not in flag translation table in: src/arch/arm/linux/linux.cc
You can certainly try to add it, however I'm skeptical that it's going to fix
The endianess of the data depends on the target being simulated. Alpha is
little endian, so it is in little endian format.
Ali
On Apr 26, 2012, at 7:59 AM, 健勇 张 wrote:
> Hi,
>
> I am running M5 in Alpha SE mode, I want to figure out what is the format of
> the data in a Packet which is transm
Just like the error says, it can't find the system files. Assuming you've
downloaded the files somewhere you'll need to set the M5_PATH environment
variable to point to them.
Ali
On Apr 28, 2012, at 11:09 AM, Thomas, Amanda J wrote:
> ImportError: Can't find a path to system files.
__
You likely don't have a compiler installed. Have you installed gcc and g++?
Ali
On Apr 29, 2012, at 8:22 PM, Bojun Ma wrote:
> Hi,All
> When I try to compling gem5,
>
> %scons build/ALPHA/m5.debug
>
> It shows that:
> You're missing the gem5 style hook, which automatically checks your code
rlying
> functions. It could also be it changes how/when stdio is buffered.
>
> Gabe
>
>
> On 04/28/12 08:03, Ali Saidi wrote:
>>
>> The error message is printed with hex and the flags are listed with octal,
>> so they're not the same. It's complaining a
Hi Amin,
Are you using gem5 stable or development? There was a bug
that might explain this that was fixed about 5 weeks ago in the
development repository.
Thanks,
Ali
On 30.04.2012 07:55, Ali Saidi
wrote:
> Hi Amin,
> I'd really like to know what is going on. It all
should
fpu=vfpv3
-mfloat-abi=softfp -static util/m5/m5op_arm.S -Iutil/m5 hello.c -o hello
-Wall
>
> Let me know if you need more information. I am new to Gem5,
so it is possible that I am doing something wrong.
>
> Thanks,
>
Amin
>
> On Mon, Apr 30, 2012 at 1:13 PM, Ali Saidi wrote
If you want to do this you can apply the following patch:
diff -r
839eeb3fcdf8 util/m5/m5op_arm.S
--- a/util/m5/m5op_arm.S Mon Apr 30
10:23:46 2012 -0500
+++ b/util/m5/m5op_arm.S Mon Apr 30 16:50:41 2012
-0500
@@ -41,14 +41,26 @@
* Ali Saidi
* Chander Sudanthi
*/
+.syntax
unified
+#ifdef
Only use code is logged, but nothing about the thread id. Since it's
an overloaded term it depends a lot on what you want process id? linux
thread id? address space identifier? If you add ExecAsid you'll get the
address space identifier for ARM. You'd need to implement that
functionality for ano
It shouldn't matter. I don't believe there have been any changes to
this between stable and dev. Using printf and the cout based printing at
once may be causing issues and is generally dangerous. You should
probably use DPRINTFN() which should work just fine.
Ali
On
02.05.2012 09:55, Edward
ntries, which is why the instList size generally has a max
of about 192 instructions. The dynamic instruction counts (seen in the
dramsim2 plot) seem to also imply that instructions are incorrectly been
removed from the ROB, and then from the cpu's instruction list in
cpu.cc, which allows more and
Hi Rio,
You'll need to enable the debug flags (specifically Exec,
Fetch, and Decode) to understand what the instruction that is being
decoded is and where it's coming from. If you're taking a checkpoint you
need to do it without caches in the system. It's possible that this
could be the cause
Here's a trace file:
>
>
http://dl.dropbox.com/u/2953302/gem5/tlb.out [26]
> To reduce size, I
just have lines that have either TLB or walker in them.
> I do see only
a handful of instruction TLB misses.
>
> -Andrew
>
> On Wed, May 2,
2012 at 11:10 AM, Ali Saidi
ning a new trace now.
>
-Andrew
>
> On Wed, May 2, 2012 at 5:28 PM, Ali Saidi wrote:
>
>> Something is wrong well before this point. There is
no reason that address 0x0 or 0x4 should be translated.
>>
>> Did you
happen to create a checkpoint when caches were in
ith an O3 CPU with caches. From what I recall reading, caches don't get
restored from checkpoints. Since the checkpoint wasn't during the
benchmark run, I assumed that was okay.
> -Andrew
>
> On Wed, May 2,
2012 at 9:07 PM, Ali Saidi wrote:
>
>> You
haven't
nt
>>> afterwards to decrease the time needed to run simulations to debug this
>>> problem. I'll create a new checkpoint, then send the new trace output.
>>>
>>> -Andrew
>>>
>>>
>>> On Wed, May 2, 2012 at 9:53 PM, Ali Saidi
Hi Amin,
If you don't change the state of the cache, writes in the functional state
won't update values in the cache which will cause problems. Similarly, if you
disconnect the caches from the system any dirty data in there won't get picked
up by the functional cpu which would be a problem. To
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