The error is that there are more that 1500 instructions currently in flight in the system. It could mean several things:
1. The value is somewhat arbitrarily defined and maybe there are more than 1500 in your system at one time? 2. Instructions aren't being destroyed correctly You could try to to run a debug binary so you'll get a list of instructions when it happens or increase the number which may be appropriate for certain situations (but 1500 is quite a few inflight instructions). Ali On 13.03.2012 10:56, Andrew Cebulski wrote: > Hi Xiangyu, > I just started looking into this some more. So at first I thought it was due to updating to a more recent revision, but then I went back to revision 8643, added your patch, built and ran....and now get the error with it too (when running ARM_FS/gem5.opt). I"m testing now to see if an update to SWIG might have resulted in this error, maybe someone on the mailing list would know if that's possible. The difference is 1.3.40 vs. 2.0.3, both of which are supported according to the dependencies wiki page. > Just for completeness, here's the error from revision 8643: > build/ARM_FS/cpu/base_dyn_inst_impl.hh:149: void BaseDynInst::initVars() [with Impl = O3CPUImpl]: Assertion `cpu->instcount > I have not tried running with gem5.debug, so I will be doing that today. Maybe this is an assertion that is occurring due to an optimization. That would mean it wouldn't be triggered in gem5.debug since it runs without optimizations. Have you tested all debug, opt and fast with your tests? > Thanks, > Andrew > > On Tue, Mar 13, 2012 at 1:37 PM, Rio Xiangyu Dong <riosher...@gmail.com [8]> wrote: > >> Hi Andrew, >> >> I didn't see this error in my simulations. May I ask which gem5 version you are using? I find some of the latest code updates do not comply with my changes. I am still using the DRAMsim2 patch on Gem5 repo8643, and have run all the runnable benchmarks in SPEC2006, SPEC2000, EEMBC2, and PARSEC2 on ARM_SE. >> >> Thank you! >> >> Best, >> >> Xiangyu >> >> FROM: Andrew Cebulski [mailto:af...@drexel.edu [5]] >> SENT: Thursday, March 08, 2012 6:52 PM >> >> TO: gem5 users mailing list CC: riosher...@gmail.com [6]; sa...@umich.edu [7] >> >> SUBJECT: Re: [gem5-users] A Patch for DRAMsim2 Integration >> >> Xiangyu, >> >> I've been having an issue recently with the number of instructions I've been seeing committed to the CPU (I have a separate thread on this). It turns out the issue seems to be coming from this patch you created to integrate DramSim2 with Gem5. Unfortunately, I've been running with gem5.fast, not gem5.opt. So up until now, I haven't been seeing assertions. I thought I'd run it with gem5.opt or debug back in December, but I must not have. My runs on the Arm O3 cpu fails with this assertion: >> >> build/ARM/cpu/base_dyn_inst_impl.hh:149: void BaseDynInst::initVars() [with Impl = O3CPUImpl]: Assertion `cpu->instcount >> >> -Andrew >> >>> Date: Sun, 18 Dec 2011 01:48:58 -0800 >>> From: "Dong, Xiangyu" <riosher...@gmail.com [1]> >>> To: "gem5 users mailing list" <gem5-users@gem5.org [2]> >>> Subject: [gem5-users] A Patch for DRAMsim2 Integration >>> Message-ID: gmail.com> >>> Content-Type: text/plain; charset="us-ascii" >>> >>> Hi all, >>> >>> I have a Gem5+DRAMsim2 patch. I've tested it under both SE and FS modes. >>> I'm willing to share it here. >>> >>> For those who have such needs, please go to my website >>> www.cse.psu.edu/~xydong [3] to download the patch and test it. To enable >>> DRAMSim2, use se_dramsim2.py script instead of se.py (for FS, you can create >>> by yourself). The basic idea to enable the DRAMsim2 module is to use the >>> derived DRAMMemory class instead of PhysicalMemory class. >>> >>> Please let me know if there are bugs. >>> >>> Thank you! >>> >>> Best, >>> >>> Xiangyu Dong >>> >>> -------------- next part -------------- >>> An HTML attachment was scrubbed... >>> URL: <http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20111218/f3fdf5da/attachment.html [4]> > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org [9] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [10] Links: ------ [1] mailto:riosher...@gmail.com [2] mailto:gem5-users@gem5.org [3] http://www.cse.psu.edu/~xydong [4] http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20111218/f3fdf5da/attachment.html [5] mailto:af...@drexel.edu [6] mailto:riosher...@gmail.com [7] mailto:sa...@umich.edu [8] mailto:riosher...@gmail.com [9] mailto:gem5-users@gem5.org [10] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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