Hi,
We are working on implementing a replacement policy in the gem5. This
policy actually keeps track (i.e., history) of the memory references from
the LD/ST instructions in order to train the predictor. Also, it predicts
which cache blocks to evict and what other blocks from later memory levels
t
Hello,
We’re still looking forward to responses.
--
*Best,Abdelrahman Hussein*
On Fri, Nov 26, 2021 at 1:51 PM Abdelrahman S. Hussein <
abdelrahman.sob...@gmail.com> wrote:
> Hi,
>
> We are working on implementing a replacement policy in the gem5. This
> policy actually keeps track (i.e., his
Hello,
I am trying to warm up my gem5 in order to train cache prediction. I am
doing this by running a timed simulation in order to limit the number of
instructions executed (if there is a more direction, that would be
certainly welcomed).
So, how to do this?
I tried the following:
system.setMe
s?
>
> Cheers,
> Jason
>
> On Sat, Dec 4, 2021 at 11:43 PM Abdelrahman S. Hussein via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hello,
>>
>> I am trying to warm up my gem5 in order to train cache prediction. I am
>> doing this by running a time
Hello,
I am working on implementing a specific cache replacement policy. This
policy basically relies on building/collecting the history of both memory
references (load/store addresses). Also, it operates using the associating
hashed PC of the load/store instructions themselves. So, code-wise, it
Hello,
I am trying to run gem5 in FS mode using the following command (I am using
gem5 v21.2):
gem5/build/X86/gem5.opt
gem5/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py --image
spec-2017/disk-image/spec-2017/spec-2017-image/spec-2017 --benchmark
503.bwaves_r --size test
However, I
Thank you so much.
There were some questions that you missed at the end of the email. I list
them below again for convenience:
- Is there a better way you can suggest using SPEC2017 in FS mode to
evaluate my system on gem5?
- My understanding is that the FS simulation is significantly s
Hello,
I am trying to build older version(s) of gem5 (specifically, the ones used
for InvisiSpec and STT). I understand that this version of gem5 requires
python2, thus, I build a virtual environment based on python2 and
re-installed scons. However, when I run this command:
scons build/X86_MESI_Tw
Hi,
I am seeking to generate multiple trace files for multi-threaded workloads
that run in FS (Full-System simulation mode). My plan is to configure the
simulation to have multiple cores, boot the image, run the workload, and
record the traces of instructions that run on each core, such that each
that information (i.e., the StaticInst
> class). You can extend the trace formats as well by modifying that code.
>
> Cheers,
> Jason
>
> On Fri, Sep 8, 2023 at 5:19 PM Abdelrahman S. Hussein via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hi,
>>
>>
Hello,
I am considering using ARM ISA for simulation on gem5. I understand that
SMT is NOT supported for Full System Simulation for x86. I just would like
to know if gem5 supports SMT for Full System simulation in ARM ISA.
Thanks
___
gem5-users mailing
Hi,
I am working on fetch.cc of the O3 CPU src directory. I am looking at
curMacroop which is declared as "StaticInstPtr" . I am working with *x86
ISA.*
For each fetched macroop represented by curMacroop, I need to get the
instruction size and the hex representation (machine code of the
instructi
For x86, check this ticket: https://gem5.atlassian.net/browse/GEM5-332
For ARM: I got this response from Giacomo Travaglini almost a month ago on
this mailing list:
Hi all,
>
>
>
> You can in principle try to setup an SMT simulation for the O3CPU by
> tweaking the smt parameters of the CPU [1]
>
Hi,
I am working on x86 Full System simulation. My goal is to get the process
name (eg. /root/my_prog.elf) that runs within the simulated image for the
current instruction being simulated. Also, I would like to get the PID as
well.
I tried the following under the arch/x86/TLB.cc:: translate()
Pro
Hello,
I am trying to run CloudSuite on FullSystem Simulation using x86 ISA.
Q1) I would like to know if gem5 can simulate such a benchmark suite
(CloudSuite) in Full System simulation.
Q2) Also, I would like to know if starting/using Docker inside the
simulated system in the FS mode is supporte
ty.
> Start with basic FS simulation, then introduce CloudSuite, and finally
> attempt Docker integration.
>
> Feel free to ask more specific questions if you encounter particular
> issues or need guidance on specific aspects of setting up or running your
> simulation!
>
> On T
Hello,
I am trying to run Cassandra benchmark from the Dacapo benchmark suite. I
am using gem5 v23.0.1 and the simulation is full system X86 ISA.
During the initialization phase of the Cassandra benchmark during the
simulation on gem5, I encountered this error:
```shell
: getrandom indicates that
Hello,
I am looking at the AtomicSimpleCPU code in src/cpu/simple for x86 ISA. I
am trying to understand the following code snippet. Whenever this condition
is true for a given PC, it does NOT follow the regular fetch from the
instruction cache and then decode. This results in a macroop called
`Mi
Hi,
I am working on the x86 page walker in gem5. I understand that the page
walker accesses the page walker cache (PWC) first and, in case of a miss,
it accesses the memory hierarchy (L1, then L2, then L3 caches and lastly
the memory). This happens through the packetpointer *read*, which reads the
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