Hi again, I am working on this flow already, such that I generate traces for x86 64-bit (i.e., x64) binaries in FS mode using O3 CPU, and I have a few follow-up questions.
*(Q1) * How can I access the instruction hexadecimal representation? For example, if I have the following instructions: mov rdi,rsp I would like to be able to get this: 48 89 e7 I am doing this in the commit.cc file where after the rob head instruction is read, I would like to get this data. The head_inst is declared as a dynamic instruction, which has staticInst field. From there, my attempts were not successful to access the hexadecimal representation of the instruction. *(Q2)* If I would like to get the number of operands (either 0, 1, or 2) for any addressing mode, is it the sum of the return values of numSrcRegs and numDestRegs? *(Q3)* I tried the disassemble function under the StaticInst class to disassemble the rob head instruction at the commit stage "head_inst-> staticInst->disassemble(head_inst->physEffAddr)". However, this ended up giving some confusing instructions, such as mov rdi, rdi, rsp. My understanding is that MOV takes only two operands. Not sure where the third came from. Also, limm t1, 0xffffffffffa0f77b, which I cannot recognize as x86 instruction. So, how does this function actually work? Thanks, -- *Best,Abdelrahman Hussein* On Tue, Sep 12, 2023 at 12:06 PM Jason Lowe-Power <ja...@lowepower.com> wrote: > Hi Abdelrahman, > > Thank you for your questions on the mailing list. I will try to answer > them as best as I can. > > - The trace CPU model was not designed to support multithreaded > applications or multiple cores. It was only tested with single-threaded > benchmarks in both SE and FS mode. Therefore, generating multiple trace > files for different threads/cores may not work as expected or may cause > errors. > - The O3 CPU is capable of traces, but I don't know if/how that will work > with multiple cores. You'll have to dig in and modify the code, most likely. > - Instructions should already have that information (i.e., the StaticInst > class). You can extend the trace formats as well by modifying that code. > > Cheers, > Jason > > On Fri, Sep 8, 2023 at 5:19 PM Abdelrahman S. Hussein via gem5-users < > gem5-users@gem5.org> wrote: > >> Hi, >> >> I am seeking to generate multiple trace files for multi-threaded >> workloads that run in FS (Full-System simulation mode). My plan is to >> configure the simulation to have multiple cores, boot the image, run the >> workload, and record the traces of instructions that run on each core, such >> that each core/thread has its own trace file. My end goal is to have a >> number of trace files, each represent a core or a thread. >> >> Questions: >> >> - Is gem5 capable of generating multiple trace files? >> - I am checking the Trace CPU Model page on gem5 >> <https://www.gem5.org/documentation/general_docs/cpu_models/TraceCPU> >> website. It has this statement "The traces have been developed for >> single-threaded benchmarks simulating in both SE and FS mode". Does this >> mean generating multiple trace files for different threads/cores >> is unsupported by gem5? >> - Is the O3 CPU capable of recording such traces? The goal is to >> generate traces using an Out-of-Order superscalar CPU. >> - I may have to add a few more fields to the instruction class, such >> as a boolean variable to check if the instruction is a branch for example. >> which file(s) should I look at? >> >> >> Looking forward to your answer. >> >> Thanks, >> ~Abdelrahman >> >> -- >> >> *Best,Abdelrahman Hussein* >> >> _______________________________________________ >> gem5-users mailing list -- gem5-users@gem5.org >> To unsubscribe send an email to gem5-users-le...@gem5.org >> >
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