For x86, check this ticket: https://gem5.atlassian.net/browse/GEM5-332
For ARM: I got this response from Giacomo Travaglini almost a month ago on this mailing list: Hi all, > > > > You can in principle try to setup an SMT simulation for the O3CPU by > tweaking the smt parameters of the CPU [1] > > In practice this has not been tested in a long time and it is very likely > it is broken. > > > > Kind Regards > > > > Giacomo > > > > [1]: https://github.com/gem5/gem5/blob/stable/src/cpu/o3/BaseO3CPU.py#L177 > -- *Best,Abdelrahman Hussein* Graduate Student School of Computing Sciences Simon Fraser University, Canada On Tue, Nov 14, 2023 at 1:13 AM Li, Zelong [COM S] via gem5-users < gem5-users@gem5.org> wrote: > Hello, > > I am currently working on replicating a side-channel attack related to SMT > port contention. I would like to clarify whether SMT is exclusively > supported in SE mode or if it is also applicable for testing in FS mode. > Any guidance or assistance on this matter would be greatly appreciated. > > Regards, > Zelong > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org >
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