[gem5-users] Ruby SLICC network vs RubyCache latency mechanics

Hi Folks, I am currently working on modeling a system in which the L3 Cache is dynamically set. As a simple example of this, say there were two sets of addresses. If I get a LD/ST request to the first set, it takes twice as long as it would for retrieval in the second set. In any case, I have b

[gem5-users] Re: Ruby SLICC network vs RubyCache latency mechanics

Hi, The tag and data access latency you are seeing in \`src/mem/ruby/structures/RubyCache.py\` are actually not implemented by the RubyCache itself. Instead, SLICC machines query these parameters using the getTagLatency and getDataLatency member functions of the CacheMemory SimObject (these fu

[gem5-users] Can I use RiscvO3CPU with TSO?

I know that RISC-V assumes RVWMO. But if I want to run a TSO RISC-V implementation, can I simply set needsTSO = True in the RiscvO3CPU configuration and be done, or am I overlooking some details about using TSO in RISC-V? I need TSO because I want to enforce load->load, load->store ordering by def

[gem5-users] Unconnected Port Debugging

Hi Folks, I am working through debugging a bug I am running while trying to run syscall mode in gem5 on the Ruby MOESI_AMD_BASE protocol. To start, the bug I am running into is as follows: src/sim/port.cc:62: fatal: system.cp_cntrl0.memory: Unconnected port! A few notes to describe what I unders

[gem5-users] MESI_Two_Level forward_eviction_to_cpu question

Hi, I was experimenting with MESI_Two_Level and was trying to use it under TSO. In the L1 cache when a cache line undergoes a transition as follows, an eviction signal is not signaled to the core LSQ: I -> IS -> IS_I -> I // Transitions from IS transition({IS, IS_I}, Inv, IS_I) { fi_sendI