[gem5-users] Can I use RiscvO3CPU with TSO?

[Z HW via gem5-users]

I know that RISC-V assumes RVWMO. But if I want to run a TSO RISC-V
implementation, can I simply set needsTSO = True in the RiscvO3CPU
configuration and be done, or am I overlooking some details about using TSO
in RISC-V?
I need TSO because I want to enforce load->load, load->store ordering by
default in my program and don't want to use fences.

Thanks!

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