Re: [gem5-users] dumping periodic stats with checkpoints

Hi, Do the cores execute the same code? -- Fernando A. Endo, PhD student and researcher CEA Lab and Université de Grenoble, UJF France 2012/11/4 shervin hajiamini > Hi Ali, > > > Thank you very much for further direction. I am able to have the stats > dumped every period with respect to the

Re: [gem5-users] Need help to build custom. O3 in ARM

Hi, Maybe this could help you: http://www.hipeac.net/content/low-power-ecosystem-gem5-practical-user-experience The first lecture was about how to implement a new O3 multicore. Hope it will help you, -- Fernando A. Endo, PhD student and researcher CEA Lab and Université de Grenoble, UJF France

Re: [gem5-users] Need help to build custom. O3 in ARM

Thank you very much for quick reply Fernando Endo. . Musharaf --- On Mon, 11/5/12, Fernando Endo wrote: From: Fernando Endo Subject: Re: [gem5-users] Need help to build custom. O3 in ARM To: "gem5 users mailing list" Date: Monday, November 5, 2012, 12:11 AM Hi, Maybe this could help yo

Re: [gem5-users] video documentation

the "bench.c" shown in the videos is a file I created in order to have something to add to the mounted image for the purposes of demonstration. Ben From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of mir shan Sent: Saturday, November 03, 2012 5:10 AM To: gem5 use

Re: [gem5-users] source code documentation

It's been updated to the latest version. Ali On 04.11.2012 01:37, Hossein Nikoonia wrote: > Dear All, > > I think doxygen-generated documents of source code is located in http://www.gem5.org/docs/index.html [1] > However, It's outdated. Is there a newer version somewhere online? > I know

Re: [gem5-users] video documentation

Thanks ben for replyBut I am new user, When I follow up the cammands I couldn't reach at the final stage. Can u suggest me what alternate should I use of Bench.c or how I create that to endup the process,regardsshany --- On Mon, 5/11/12, Payne, Benjamin wrote: From: Payne, Benjamin Subject:

Re: [gem5-users] dumping periodic stats with checkpoints

bbed... > URL: < > http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20121028/a6f3c198/attachment-0001.html > > > > -- > > > ___ &

Re: [gem5-users] source code documentation

Thanks! On Mon, Nov 5, 2012 at 6:41 PM, Ali Saidi wrote: > It's been updated to the latest version. > > > > Ali > > > > On 04.11.2012 01:37, Hossein Nikoonia wrote: > > Dear All, > > I think doxygen-generated documents of source code is located in > http://www.gem5.org/docs/index.html > However,

Re: [gem5-users] dumping periodic stats with checkpoints

_ > > > gem5-users mailing list > > > gem5-users@gem5.org <http://mc/compose?to=gem5-users@gem5.org> < > http://mc/compose?to=gem5-users@gem5.org> > > > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >

[gem5-users] Feeding instruction traces into GEM5 ARM

I have traces of ARM instructions with opcode bytes. I would like to simulate it with the GEM5 simulator. How difficult is it to feed the traces into the GEM5 simulator. Xin ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman

Re: [gem5-users] Feeding instruction traces into GEM5 ARM

Another question is how difficult is this to build an interface between GEM5 and some other functional simulators such that the functional simulators feed instructions into GEM5 and GEM5 can process them by cycle accurate simulation real-time. Xin On Mon, Nov 5, 2012 at 12:59 PM, Xin Tong wrote

[gem5-users] Simple DRAM not draining when cores do not switch L1's

I have a system that repeatedly switching back and forth between core types; I am trying to evaluate the effects on the caches due to switching. I give each core its own L1 caches and when switching out, it keeps its L1s connected. However, when I upgraded to the latest repo that uses simple DRAM.

Re: [gem5-users] X86 multicore configuration files

Thank you. Do you know how to control number of cores? On Sat, Nov 3, 2012 at 3:02 PM, shermeny...@gmail.com wrote: > In the configuration script, search for physmem, you can configure the > size and the latency. > > - Reply message - > From: "Marko Zivkovic" > To: "gem5 users mailing l

Re: [gem5-users] Simple DRAM not draining when cores do not switch L1's

Hi Tony, Thanks for pointing it out. I'll have a look. Andreas From: Anthony Gutierrez mailto:atgut...@umich.edu>> Reply-To: gem5 users mailing list mailto:gem5-users@gem5.org>> Date: Monday, 5 November 2012 19:43 To: "gem5-users@gem5.org" mailto:gem5-users@gem5.org

Re: [gem5-users] Simple DRAM not draining when cores do not switch L1's

Hi Andreas, Actually, it appears the simple_dram does not drain properly at all in some cases. You should be able to reproduce this error using a clean checkout (I did add DPRINTFs to simple_dram.cc:drain()) without any modifications; the following command line is what I ran: ./build/ALPHA/m5.opt

Re: [gem5-users] Simple DRAM not draining when cores do not switch L1's

NOTE, the problem with this trace is that it hangs while trying to drain because the physmem never signals drained; it's dramWriteQueue is never emptied and only refreshes forever. -Tony ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cg

[gem5-users] Cache Trace Understanding

Hi All, I am currently trying to understand the cache trace for L2. I don't quite understand how the write request are handled. From the trace I can see ReadReq and ReadExReq. They are either miss or hits. However, I don't see any trace for 'writes' only see 'writebacks'. What are the mea