Thnx Yang
Can someone Working on multiprocessor simulation confirm that, do we need
FS mode(only) for multiprocessor simulation & rely on OS scheduling?.
Regards
Mann
On Mon, Nov 5, 2012 at 12:09 AM, sheng yang wrote:
> hi Mann,
>
> I am not using multiprocessor simulation enough to advice yo
On Sun, 4 Nov 2012, Mann wrote:
Thnx Nilay
I may be naive, not able to understand few things
wrt my previous question & Your reply
Q1. If a var is shared between two processors, How data flow happens & how
to trace the same in simulation?
You will need to learn about how caches maintaining co
hi Mann,
I am not using multiprocessor simulation enough to advice you. But this
web page may be some help to you:
http://www.m5sim.org/Multiprogrammed_workloads
From my understanding if you want one program to use multiple
processor, you need to use FS (full system) mode and rely on OS (eg.
Thanks Yang
I am doing the same to understand the flow, but I have very
basic/naive/foolish question that, when we assign a task for multiprocessor
simulation, how simulator understand/keep_info that it is shared & can you
please tell some simple multiprocessor program/example that can be
simulated
when initiate the simulation use "gem5.opt --debug-flags=Cache", it will
print the traces of cache access.
On 04/11/12 18:06, Mann wrote:
Thnx Nilay
I may be naive, not able to understand few things
wrt my previous question & Your reply
Q1. If a var is shared between two processors, How data
Thnx Nilay
I may be naive, not able to understand few things
wrt my previous question & Your reply
Q1. If a var is shared between two processors, How data flow happens & how
to trace the same in simulation?
>> You will need to learn about how caches maintaining coherence. Those .sm
files implemen
On Sat, 27 Oct 2012, Mann Mann wrote:
Thnx Nilay
2. How L1_TBEs is maintained ?
The question is unclear. You need to be more specific.
Actually I am implementing a buffer & thought to make it similar to TBE
array. I wanted to know How this array is stored & accessed ?
Take a look at t
Thnx Nilay
2. How L1_TBEs is maintained ?
>
>> The question is unclear. You need to be more specific.
Actually I am implementing a buffer & thought to make it similar to TBE
array. I wanted to know How this array is stored & accessed ?
3. I am introducing a level of cache between L1 & L2
>>Thi
On Fri, 26 Oct 2012, Mann Mann wrote:
Thanks Nilay
As you mentioned, I have gone through src/sim & mem/protocol files.
Understood how Classes & Cache is maintained but still has few questions.
It will be much helpful if get specific answers
1. If a var is shared between two processors, How data
Thanks Nilay
As you mentioned, I have gone through src/sim & mem/protocol files.
Understood how Classes & Cache is maintained but still has few questions.
It will be much helpful if get specific answers
1. If a var is shared between two processors, How data flow happens & how
to trace the same in
On Fri, 5 Oct 2012, Mann Mann wrote:
Hi All
in Shared Multiprocessor Simulation, I understood that simulator assigns
sequencer to each process, but I need to grab exact flow,
I want to understand how shared variables are used, and how data flow
between these processors.
(In detail : How virtual/
Hi All
in Shared Multiprocessor Simulation, I understood that simulator assigns
sequencer to each process, but I need to grab exact flow,
I want to understand how shared variables are used, and how data flow
between these processors.
(In detail : How virtual/physical page mapping is maintained in s
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