Thanks Yang
I am doing the same to understand the flow, but I have very
basic/naive/foolish question that, when we assign a task for multiprocessor
simulation, how simulator understand/keep_info that it is shared & can you
please tell some simple multiprocessor program/example that can be
simulated for understanding.

Regards
Mann


On Sun, Nov 4, 2012 at 11:47 PM, sheng yang <shermeny...@gmail.com> wrote:

>  when initiate the simulation use "gem5.opt --debug-flags=Cache", it will
> print the traces of cache access.
>
>
> On 04/11/12 18:06, Mann wrote:
>
> Thnx Nilay
>
>  I may be naive,  not able to understand few things
> wrt my previous question & Your reply
> Q1. If a var is shared between two processors, How data flow happens & how
> to trace the same in simulation?
> >> You will need to learn about how caches maintaining coherence. Those
> .sm files implement the coherence protocol. You can use debug flags to
> figure out how communication takes place between different caches.
>
>  I have going throgh protocol/.sm files to understand Coherency & data
> flow but couldn,t figure out:
> - How simulator understands that a variable is shared?
> - Can you refer Some simple multiprocessor program for simulation so that
> I can observe data flow between caches.
>
>  Regards
> Mann
>
> On Fri, Oct 5, 2012 at 12:49 PM, Mann Mann <evebu...@gmail.com> wrote:
>
>> Hi All
>> in Shared Multiprocessor Simulation, I understood that simulator assigns
>> sequencer to each process, but I need to grab exact flow,
>> I want to understand how shared variables are used, and how data flow
>> between these processors.
>> (In detail : How virtual/physical page mapping is maintained in simulator)
>> Could somebody suggest, where to look for this info.
>>
>>  Regards
>>  Mann
>>
>
>
>
>  --
> Cheers...........
> Mann
>
>
>
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-- 
Cheers...........
Mann
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