Thanks Mahita for spotting a real bug. I have posted a fix [1]; hopefully it
will be backported to gem5 v21.1
Kind regards
Giacomo
[1]: https://gem5-review.googlesource.com/c/public/gem5/+/51407
> -Original Message-
> From: Mahita Nagabhiru
> Sent: 01 October 2021 20:07
> To: Giacomo
Hi Giacomo,
Looks like the regStats() function in HTMSequencer was interfering with
ClockedObject::regStats() in AbstractController.cc; not fully sure what
both regStats do but I commented regStats() out from HTMSequencer
and the HTM part seems to be working now. I need to look into extending CAS
Hi Mahita,
Could you debug it with gdb and let us know which stat gets initialized twice?
Kind Regards
Giacomo
> -Original Message-
> From: Mahita Nagabhiru
> Sent: 29 September 2021 12:00
> To: Giacomo Travaglini
> Cc: gem5 users mailing list
> Subject: Re: [gem5-users] Support for
Thanks a lot Giacomo.
By default (without ruby), I am able to run my microbenchmark now;
but I am trying to use the ruby side for memory modelling- I need to model
CAS using that and also be able to use ARM HTM feature but when I run using
"--ruby", I get the following panic message:
*"build/ARM_ME
Hi Mahita,
Yes Armv8.1-LSE is implemented and therefore you should be able to use CAS
ISA definition of CAS:
https://github.com/gem5/gem5/blob/stable/src/arch/arm/isa/insts/amo64.isa#L226
System level switch for LSE:
https://github.com/gem5/gem5/blob/stable/src/arch/arm/ArmSystem.py#L75
As you
