Hi Giacomo, Looks like the regStats() function in HTMSequencer was interfering with ClockedObject::regStats() in AbstractController.cc; not fully sure what both regStats do but I commented regStats() out from HTMSequencer and the HTM part seems to be working now. I need to look into extending CAS to work with ruby next- so I will reach out again when I get stuck.
On Thu, Sep 30, 2021 at 5:07 PM Giacomo Travaglini < giacomo.travagl...@arm.com> wrote: > Hi Mahita, > > Could you debug it with gdb and let us know which stat gets initialized > twice? > > Kind Regards > > Giacomo > > > -----Original Message----- > > From: Mahita Nagabhiru <mnag...@ncsu.edu> > > Sent: 29 September 2021 12:00 > > To: Giacomo Travaglini <giacomo.travagl...@arm.com> > > Cc: gem5 users mailing list <gem5-users@gem5.org> > > Subject: Re: [gem5-users] Support for CAS (compare and swap) instruction > in > > ARM arch > > > > Thanks a lot Giacomo. > > By default (without ruby), I am able to run my microbenchmark now; but I > > am trying to use the ruby side for memory modelling- I need to model CAS > > using that and also be able to use ARM HTM feature but when I run using > "-- > > ruby", I get the following panic message: > > "build/ARM_MESI_Three_Level_HTM/base/statistics.hh:953: fatal: fatal > > condition check() occurred: Stat has already been initialized" > > I have attached a log-file is that helps. > > I tried inspecting the usual files like > > src/mem/ruby/structures/CacheMemory.* , Sequencer, HtmSequencer etc > > but I cannot find the cause. > > I was able to use the HTM feature on the 20.1 stable version of gem5; so > I am > > trying to do a diff between the latest files and the working version and > I saw > > most changes were to accommodate the statistics base class correctly. > > I am not very well versed with gem5, so I'm really struggling to figure > out the > > cause. Any suggestions? > > > > On Tue, Sep 28, 2021 at 3:50 PM Giacomo Travaglini > > <giacomo.travagl...@arm.com <mailto:giacomo.travagl...@arm.com> > > > wrote: > > > > > > Hi Mahita, > > > > Yes Armv8.1-LSE is implemented and therefore you should be able to > > use CAS > > > > ISA definition of CAS: > > https://github.com/gem5/gem5/blob/stable/src/arch/arm/isa/insts/amo64.i > > sa#L226 > > System level switch for LSE: > > https://github.com/gem5/gem5/blob/stable/src/arch/arm/ArmSystem.py#L > > 75 > > > > As you can see we support it by default so you should be able to > use > > it with no modification needed > > > > Kind Regards > > > > Giacomo > > > > > -----Original Message----- > > > From: Mahita Nagabhiru via gem5-users <gem5-users@gem5.org > > <mailto:gem5-users@gem5.org> > > > > Sent: 28 September 2021 15:42 > > > To: gem5-users@gem5.org <mailto:gem5-users@gem5.org> > > > Cc: Mahita Nagabhiru <mnag...@ncsu.edu > > <mailto:mnag...@ncsu.edu> > > > > Subject: [gem5-users] Support for CAS (compare and swap) > > instruction in > > > ARM arch > > > > > > Hi, > > > > > > I am trying to experiment with lock-free data structures and one > of > > the key > > > instructions in my microbenchmarks is CAS (compare and swap) > > instruction. I > > > need this in ARM architecture; I saw that gem5 page says LSE > > extensions are > > > supported but I cannot find anything relevant in the "src/" > directory > > on a > > > quick grep except for a line in a config life: > > src/arch/arm/ArmSystem.py. Am I > > > missing something here? Is there a guideline as to how to add > > support for an > > > instruction for aarch64 in case it is not present? > > > Any help would be highly appreciated! > > > > > > > > > -- > > > > > > Mahita Nagabhiru > > IMPORTANT NOTICE: The contents of this email and any attachments > > are confidential and may also be privileged. If you are not the intended > > recipient, please notify the sender immediately and do not disclose the > > contents to any other person, use it for any purpose, or store or copy > the > > information in any medium. Thank you. > > > > > > > > > > -- > > > > Mahita Nagabhiru > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > -- Mahita Nagabhiru
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