Hi Mahita, Yes Armv8.1-LSE is implemented and therefore you should be able to use CAS
ISA definition of CAS: https://github.com/gem5/gem5/blob/stable/src/arch/arm/isa/insts/amo64.isa#L226 System level switch for LSE: https://github.com/gem5/gem5/blob/stable/src/arch/arm/ArmSystem.py#L75 As you can see we support it by default so you should be able to use it with no modification needed Kind Regards Giacomo > -----Original Message----- > From: Mahita Nagabhiru via gem5-users <gem5-users@gem5.org> > Sent: 28 September 2021 15:42 > To: gem5-users@gem5.org > Cc: Mahita Nagabhiru <mnag...@ncsu.edu> > Subject: [gem5-users] Support for CAS (compare and swap) instruction in > ARM arch > > Hi, > > I am trying to experiment with lock-free data structures and one of the key > instructions in my microbenchmarks is CAS (compare and swap) instruction. I > need this in ARM architecture; I saw that gem5 page says LSE extensions are > supported but I cannot find anything relevant in the "src/" directory on a > quick grep except for a line in a config life: src/arch/arm/ArmSystem.py. Am I > missing something here? Is there a guideline as to how to add support for an > instruction for aarch64 in case it is not present? > Any help would be highly appreciated! > > > -- > > Mahita Nagabhiru IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
