Hi gem5 users,
I am working with my team to set up a CPU model and I am having some trouble
making sense of how the core settings are handled.
The core configurations (for example, o3_arm_v7a.py [1]) allow (require?)
specifying parameters for the various components (for example, size,
associ
Hi Arthur Perais,
Many thanks for explanation.
I have kept all the delay parameters to 1 except renameToIEWDelay=2.
Looks like there is already fetch queue between fetch and decode. This was
added to decouple fetch & decode stages.
http://reviews.gem5.org/r/2297/diff/1/
Based on above, I added a
Ideally, you would want to have queues between Fetch and Decode and
Decode and Rename, but instead we have skidBuffers that are dimensioned
to absorb instructions inflight between stages in case of a blocking event.
So as you point out, while there is still space in the the decode
skifBuffer, Fe
Hi Arthur Perais,
Thanks for your response. I have a question regarding blocking & unblocking
of decode stage.
Could you please help me in understanding them.
I am working on a O3 CPU model with below configuration
fetchToDecodeDelay = 1
fetchWidth = 8
decodeToFetchDelay=1
decodeWidth = 4
skid-b
- Mail original -
> De: "Virendra Kumar Pathak"
> À: gem5-users@gem5.org
> Envoyé: Dimanche 1 Novembre 2015 16:25:39
> Objet: Re: [gem5-users] CPU Configuration
> Hi,
> I have similar doubt regarding extending the number of pipeline stages in
> gem5.
>
Hi,
I have similar doubt regarding extending the number of pipeline stages in
gem5.
I am trying to extend default 7-stage o3 cpu pipeline to 15-stage.
Any guidance on below questions will be highly appreciated.
1) How the delay parameters like decodeToFetchDelay & fetchToDecodeDelay
are used in
Thanks for your information.
May I say it defines an index from which slot in the timeBuffer to get
data, like following
fromCommit = timeBuffer->getWire(-commitToIEWDelay);
I'm still curious what's the content stored in timeBuffer and how it's
related to different number of pipe stages.
On Wed
Hello,
I think these parameters define the number of cycles which a message takes
going from stage A to stage B (AtoBDelay). They're related to 'Time
Buffers', used to simulate a variable number of pipeline stages.
Regards,
--
Fernando A. Endo, PhD student and researcher
Université de Grenoble,
It's interesting to see following setting in config.ini file.
Why there are 2 delay defined between decode and fetch stage?
[system.cpu]
type=DerivO3CPU
decodeToFetchDelay=1
fetchToDecodeDelay=3
.
.
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