Hi, I have similar doubt regarding extending the number of pipeline stages in gem5. I am trying to extend default 7-stage o3 cpu pipeline to 15-stage.
Any guidance on below questions will be highly appreciated. 1) How the delay parameters like decodeToFetchDelay & fetchToDecodeDelay are used in modeling the pipeline stages? Look like fetchToDecodeDelay & fetchWidth are used in calculating skidBufferMax. And decodeToFetchDelay is linked with timeBuffer. Below is the snippet code from cpu/o3/fetch_impl.hh line 77: skidBufferMax = (fetchToDecodeDelay + 1) * params->fetchWidth; line 187: fromFetch = fetchQueue->getWire(-fetchToDecodeDelay); But I am confused how they increase the number of pipeline stages. 2) In gem5, At which stage Unified scheduler or reservation station is implemented ? Is it implemented by instruction queue itself ? Thanks in advance for your time. with regards, Virendra Kumar Pathak
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