Thanks for your information. May I say it defines an index from which slot in the timeBuffer to get data, like following fromCommit = timeBuffer->getWire(-commitToIEWDelay);
I'm still curious what's the content stored in timeBuffer and how it's related to different number of pipe stages. On Wed, Jul 24, 2013 at 4:05 AM, Fernando Endo <fernando.en...@gmail.com>wrote: > Hello, > > I think these parameters define the number of cycles which a message takes > going from stage A to stage B (AtoBDelay). They're related to 'Time > Buffers', used to simulate a variable number of pipeline stages. > > Regards, > > -- > Fernando A. Endo, PhD student and researcher > > Université de Grenoble, UJF > France > > > > 2013/7/17 Jianghao <guojh...@gmail.com> > >> It's interesting to see following setting in config.ini file. >> Why there are 2 delay defined between decode and fetch stage? >> >> [system.cpu] >> type=DerivO3CPU >> decodeToFetchDelay=1 >> fetchToDecodeDelay=3 >> . >> . >> ______________________________**_________________ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/**mailman/listinfo/gem5-users<http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users> >> > > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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