[gem5-users] (no subject)

Hello everyone Is there any way to make a router to drop a packet while routing? ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

Hi, I am new to gem5 and I was trying to run multiple benchmarks on gem5 to get some results for my research. I face a issue that whenever I run multiple gem5 simulations on one disk image, some of the gem5 process exits without giving any results or errors. For example, I have about 20 microbenc

[gem5-users] (no subject)

Hi, I'm trying to run multiworkload smt. I an the hello world program from tests, and I see that one of the outputs is displayed after m5exit. What is the reason for this? ./build/X86/gem5.opt ./configs/example/se.py --smt --cpu-type=DerivO3CPU --caches -c tests/test-progs/hello/bin/x86/linux/he

Re: [gem5-users] (no subject)

Thank you so much. I'll try this. On Sun, May 12, 2019 at 10:22 PM Abhishek Singh < abhishek.singh199...@gmail.com> wrote: > Hello Nazish, > > If you are using classic memory, edit src/mem/cache/base.cc file’s > recvTimingReq function. > You can access the old data through blk->data and the new d

Re: [gem5-users] (no subject)

Your logic sounds correct to me for single core. For multi core, the last level cache is shared, and you can get block from other core’s L1 dcache. So you need to think through about what behavior you are expecting from your design and make changes or keep things same. On Mon, May 13, 2019 at 12:

Re: [gem5-users] (no subject)

Dear Abhishek, Many thanks for your reply. I will set the flag in response packet for L2 hit. This flag will be default reset, therefore, I think I will not need main memory flag in this case. Please, let me know if you feel a problem in this logic. For multicore simulation, what sh

Re: [gem5-users] (no subject)

Hello Nazish, If you are using classic memory, edit src/mem/cache/base.cc file’s recvTimingReq function. You can access the old data through blk->data and the new data by pkt->getdata(this you need to search in src/mem/packet.hh, I may have made mistake in writing correct name of the function). O

[gem5-users] (no subject)

Hello! I am relatively new to gem5 and trying to implement an encoding scheme in it but not exactly sure what the best approach to implementing this would be. The way i would like this to work is when there is a write access to the last level cache, we need to read the old data in the last level

Re: [gem5-users] (no subject)

What you do, is create flags in src/mem/packet.hh for various cache levels. Whenever you hit in L2, you can set the L2flag in response pkt. And if it is misses in L2, set main memory flag in response pkt, as you are sure you will get data from main memory. Here we are assuming it’s a single core si

Re: [gem5-users] (no subject)

Hi Muhammad, One way is to use the function "name()" in src/mem/cache/base.cc and src/mem/cache/cache.cc file to implement cache specific function. For e.g., for implementing things specifically for dcache u can just write if (name() == "system.cpu.dcache"){ } Best regards, Abhishek On F

[gem5-users] (no subject)

Dear All, 1- For blocks loaded in the L1 cache, how can I distinguish that it was loaded into the L1 cache from the L2 cache (L2 hit) or main memory (L1 cache)? Many thanks, Best Regards, Avais ___ gem5-users mailing list gem5-users@gem5.org http://m5si

Re: [gem5-users] (no subject)

Dear All, I have one question. For blocks loaded in the L1 cache, how can I distinguish that it was loaded into the L1 cache from L2 cache or main memory? Many thanks, Best regards, Avais On Wed, May 8, 2019 at 5:21 AM Abhishek Singh < abhishek.singh199...@gmail.com> wrote: > Hi Muham

Re: [gem5-users] (no subject)

Dear Abhishek, Many thanks for the useful response, I will try to modify clean victim eviction from "dcache". Many thanks, Best regards, Avais On Wed, May 8, 2019 at 5:21 AM Abhishek Singh < abhishek.singh199...@gmail.com> wrote: > Hi Muhammad, > > > If you want on L2 hit, the block i

Re: [gem5-users] (no subject)

Hi Muhammad, If you want on L2 hit, the block is invalidated from L2 cache and filled in Dcache and the rest behavior same as you explained in the diagram, you can use gem5's "most_excl" option in "gem5/src/mem/cache/Cache.py" file. You may need to take care of "clean victim" from dcache which is

[gem5-users] (no subject)

Dear All, Is 'mostly exclusive cache' supported in GEM5 classic model strictly non-exclusive cache? If it is not non-exclusive cache, how can I make it non-exclusive cache? The non-exclusive cache is shown in Fig. below. [image: image.png] Can anyone guide me? Many thanks, best r

[gem5-users] (no subject)

Hi there, I trying to run a binary file on GEM5, but I'm getting a weird error and it is stuck on it. When I run the same binary file on my actual machine, it runs perfect. The error is highlighted in yellow bellow: ** GEM5 terminal output: *** *

[gem5-users] (no subject)

What does m_vc member of flit.hh in garnet2.0 store? Why is it used? ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

http://www.gem5.org/Garnet2.0 It is woken up by both the coherence protocol buffers and the router to NI links connected to it. Cheers, Tushar On Jun 26, 2018, 2:48 AM -0400, Nikhitha Josh , wrote: Hi, Which class calls the Network Interface wakeup() function? Regards, Nikhitha __

[gem5-users] (no subject)

Hi, Which class calls the Network Interface wakeup() function? Regards, Nikhitha ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

Hi, Where in gem5 are new objects of Message being created? Thanks, Nikhitha ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

Hi, I'm a beginner in gem5 and I'm trying to create my own packet and send it from a certain source to a certain destination. I'm finding some trouble with the net_dest component of RouteInfo structure. I cant understand the actual concept of the NetDest class. Please help me in this regard. Th

[gem5-users] (no subject)

Dear All, Has anyone made some list of read intensive or data intensive SPEC2006 benchmarks or some other benchmarks Many Thanks Best Regards Avais ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/ge

Re: [gem5-users] (no subject)

Hello yes if you are using ruby memory system you can select the type of protocol (e.g., MESI Two level, MOESI CMP Directory etc). regards, Muhammad On 11 October 2017 at 10:51, Muhammad Avais wrote: > Hi, > Does GEM5 follows any specific cache coherence protocol? > If yes? then which

[gem5-users] (no subject)

Hi, Does GEM5 follows any specific cache coherence protocol? If yes? then which one? Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

Hi, I have question regarding 'ResponseLatency' of Cache. Is it technology dependent or has fixed value? How to choose its value? Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-u

[gem5-users] (no subject)

Hi I am a new user of gem5 I want to realize a simulation of 4 benchmarks of the mibench suite, my goal is to study the shared  l2 cache and private L2 cache. I compile jpeg for ARM architecture and when I executed it with the following command I could not find the miss rate and hit rate for eac

[gem5-users] (no subject)

hii ran gem5  with 9 core and ruby memory, is it true that cpu0 and cpu1 and cpu2 send most request and the others haven't any request (in smilarge benchmark)?___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5

[gem5-users] (no subject)

help ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

Hello, I’m trying to simulate a SPARC processor with SMT enabled in SE mode. When I enable the SMT switch (using --smt --cpu-type=detailed --caches) with a single core, it works fine if there’s only one workload. If I add a second workload, though, I get an assertion error that “params->numPh

[gem5-users] (no subject)

-- *Khaled M. Attia* *T.A. @ Computers & Systems Engineering* *Mansoura University, Egypt* Mob. : +201000736160 email: khaled.3ttia[at]gmail.com ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

Hello everyone, I want the benchmark of alpha to evaluate the performance of the system.Please help me. Thanks & regards Minu ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

Hi, i have my own algorithm to shared last level cache L2 that is LRR , I have implemented LRRPolicy.cc file same as like LRUPolicy and i am using two extra bits for replacing line L2, depends on the information available in L1 cache. here is the problem is how to run two separate replacem

[gem5-users] (no subject)

Hello, I am new to gem5. I have seen some earlier posts discussing generation of ruby.stat. I am using X86_MESI_Two_Level binary with config script fs.py with ruby enabled. But I don't see any such file (ruby.stat). can anyone help me with this. Regards Dhruvo

[gem5-users] (no subject)

Hi What we would do when we modified a file in gem5 repo for seeing the result of this modification!?   ---Babak Aghaei Ph.D candidate ___ gem5-users mailing list gem5-users@gem5.org http://m5s

[gem5-users] (no subject)

Hi this is possible, befor you must establish the garnet network and then run any benchmark on it. best --- Babak Aghaei Ph.D candidate ___ gem5-users mailing list gem5-users@gem5.org http://m

Re: [gem5-users] (no subject)

I've compiled Parsec v.2.1 for M5 following the instructions on http://www.cs.utexas.edu/~cart/parsec_m5/. The code changes I needed were a few, so I did not have much efforts. You should aim this using the same instructions, reading the Tech Report http://www.cs.utexas.edu/~parsec_m5/TR-09-32.pdf

[gem5-users] (no subject)

Hi Is anybody has run Parsec 3.0 on ALPHA ISA? plz help! --- Babak Aghaei Ph.D candidate in Computer Engineering (Hardware), Science and Research University Tehran, IRAN E-Mail: b.agh...@iaut.ac.ir E-Mail: babak_agha...@yahoo.com E-M

[gem5-users] (no subject)

Hi, I am using the latest stable version for x86+ruby+FS. I encountered the same assertion failure as the following email (posted in May) when I increased the memory size to 8GB. Could you please give me any suggestions? Thanks, Yingying HI everybody: I am a

[gem5-users] (no subject)

Hi All I have run the parsec all benchmarks in standalone, but in gem5, when I create the disk image for ALPHA ISA by contain parsec 3.0 and run simulation I face with the bash script problem like this: /parsec-3.0/bin/parsecmgmt:line 1288: ${BASH_VERSINFO[0]}: bad substitution /parsec-3.0/bi

[gem5-users] (no subject)

Hello, I have been trying to run Asimbench(renamed as Moby) on gem5. I made the changes to FSConfig.py as mentioned in the wiki page to boot the sdcard along with the android image. When I looked at the screenshots that are dumped into m5out, I realized that the benchmarks aren't running. For examp

[gem5-users] (no subject)

— Sent via Carrier Pigeon___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

Amin/Tony, there is a very big reason for why gem5 does this. It's about modeling what real processors do. Modern out of orders are very deeply pipelined and instructions take multiple cycles to execute from the time they are scheduled. To enable back-to-back execution of dependent instructions,

Re: [gem5-users] (no subject)

Tony, I noticed the same thing as well and as you mentioned the perf penalty could be really high. http://www.mail-archive.com/gem5-users@gem5.org/msg05894.html I don't know what the reason could be, but I was able to fix this. If I remember right, to prevent squashing, you need to mark those load

[gem5-users] (no subject)

Hi All, Apologies in advance if this is a silly question, or a repeat. I recently noticed that the OoO core squashes itself and all younger instructions when a load is issued to the memory system, but the cache is blocked (say the MSHRs are full, or there are no targets left). Contrarily, whe

Re: [gem5-users] (no subject)

s.robsize >>>> >>>> ** ** >>>> >>>> After this, you can use the option in the command line, like >>>> >>>> ** ** >>>> >>>> gem5.opt configs/example/se.py --robsize=64 …… >>>&g

Re: [gem5-users] (no subject)

se the option in the command line, like >>> >>> ** ** >>> >>> gem5.opt configs/example/se.py --robsize=64 …… >>> >>> ** ** >>> >>> Note that if your option includes dash “-”, it will be converted into >>> und

Re: [gem5-users] (no subject)

score “_”. For example, “--rob-size” produces representative >> “options.rob_size”. >> >> ** ** >> >> Also, it is pretty helpful if you look at the Options.py to see how the >> default options are added into the system. The file is in configs/common/. >> &

Re: [gem5-users] (no subject)

> “options.rob_size”. > > > > Also, it is pretty helpful if you look at the Options.py to see how the > default options are added into the system. The file is in configs/common/. > > > > -Tao > > > > > > From: gem5-users-boun...@gem5.org

Re: [gem5-users] (no subject)

> ** ** > > *From:* gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] *On > Behalf Of *Mahshid Sedghi > *Sent:* Tuesday, July 16, 2013 4:35 PM > *To:* gem5 users mailing list > *Subject:* [gem5-users] (no subject) > > ** ** > > Hello, > >

Re: [gem5-users] (no subject)

it is pretty helpful if you look at the Options.py to see how the default options are added into the system. The file is in configs/common/. -Tao From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On Behalf Of Mahshid Sedghi Sent: Tuesday, July 16, 2013 4:35 PM To: gem5 u

[gem5-users] (no subject)

Hello, I want to introduce a new option to the simulation script to define the ROB size, since I am doing experiments with different ROB sizes and would like to skip the procedure of rebuilding the gem5 again and again for different ROB sizes. Basically, I need to do a similar thing as the thread

[gem5-users] (no subject)

Hi everyone, Some of the PARSEC benchmarks end with error: build/ALPHA/sim/eventq.cc:63: virtual Event::~Event(): Assertion `!scheduled()' failed. 181 Program aborted at cycle 242845445 182 /var/spool/PBS/mom_priv/jobs/1185438.della-pbs.SC: line 10: 10507 Aborted I followed the instruction fr

[gem5-users] (no subject)

This comment in src/arch/arm/linux/system.cc: // Task file is read by cache occupancy plotting script or // Streamline conversion script. Suggests that there are some scripts available for plotting the data in this file, or converting it to a Streamline compatible format; are these scripts availa

[gem5-users] (no subject)

Is it possible to have multiple banks in shared L2 cache with variable size(at-least 2 size)please guide me in identifying which part of the code needs to be modified. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailma

[gem5-users] (no subject)

which part of the codei should modify to implement global LRU instead of LRU for a set ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

which part of the code collects all memory reference ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] (no subject)

Hi all, I would like to know the relationship between an application binary and gem5 in FS mode. Is the binary directly fed to kernel? While running the binary file, can I still access information about threads through gem5? Or once run in fs mode gem5 can only provide trace of CPUs (about interac

[gem5-users] (no subject)

Hi All, I met a problem. I need some extra memory accesses, so I allocate the missbuffer in the timingAccess(), but this is done without any change in the time. So the memory is handling the requests very slow, so the mshr which buffers the resquests soon gets full. I think a way to solve this is

[gem5-users] (no subject)

Hi, I am using ALPHA build_opt. Am I using MI_example protocol or MOESI snooping protocol (as I am using Classic memory system, evident from "makeLinuxAlphaSystem" in FSConfig.py) Thanks, ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/c

[gem5-users] (no subject)

Hi, I am not able to build gem5 with python 2.4.3 and swig 2.0.7, even though dependencies show python : version 2.4 - 2.7 swig : version 1.3.34 or newer I was able to successfully able to build it on my laptop with python version 2.7.3, swig 2.0.4. I want to run on my lab system with centos 5.

Re: [gem5-users] (no subject)

RA (RIT Student)" mailto:sxm5...@rit.edu>> Reply-To: gem5 users mailing list mailto:gem5-users@gem5.org>> Date: Sunday, 27 January 2013 14:46 To: gem5 users mailing list mailto:gem5-users@gem5.org>> Subject: Re: [gem5-users] (no subject) I want to specify gem5 which g++ com

Re: [gem5-users] (no subject)

* Saturday, January 26, 2013 9:43 PM > *To:* gem5-users@gem5.org > *Subject:* [gem5-users] (no subject) > >Hi Everyone, > How do I set gem5 to use g++44 compiler instead of g++ compiler. I cannot > directly upgrade my gcc version 4.1.2 as I use Centos 5. > Thanks, > >

Re: [gem5-users] (no subject)

...@rit.edu] Sent: Saturday, January 26, 2013 9:43 PM To: gem5-users@gem5.org Subject: [gem5-users] (no subject) Hi Everyone, How do I set gem5 to use g++44 compiler instead of g++ compiler. I cannot directly upgrade my gcc version 4.1.2 as I use Centos 5. Thanks

[gem5-users] (no subject)

Hi Everyone, How do I set gem5 to use g++44 compiler instead of g++ compiler. I cannot directly upgrade my gcc version 4.1.2 as I use Centos 5. Thanks, ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] (no subject)

this is correct. However, there should be more tag bits for the purpose of cache conherence and replacement (e.g., valid, dirty, LRU...) -Tao On 11/24/2012 01:23 AM, Nitin Chaturvedi wrote: Dear sir srry for wrong interpretation..please check again and correct me if i am wrong

Re: [gem5-users] (no subject)

Subject: Re: [gem5-users] (no subject) Dear sir srry for wrong interpretation..please check again and correct me if i am wrong... my understanding. If..physical address space 1GB.size of physical address 30-bits... Now, 1. if size of

Re: [gem5-users] (no subject)

Dear sir srry for wrong interpretation..please check again and correct me if i am wrong... my understanding. If..physical address space 1GB.size of physical address 30-bits... Now, 1. if size of on chip L2 cache is 4MB 2. block size..

[gem5-users] (no subject)

Hello all, I'm in doubt with three parameters inside the file "mcpat-template.xml" got from https://www.cl.cam.ac.uk/~acr31/sicsa/. It's Inside the component above: ... I found that the first two values need to have "::total" appended, like this:

Re: [gem5-users] (no subject)

Sunitha, Have you installed the first software in this list? http://www.gem5.org/Dependencies#External_tools_and_required_versions On Jul 9, 2012, at 4:23 AM, sunitha p wrote: > hi all.. > > I am trying to install gem5 > am facing this error..have installed scons,swig,python.. > > kindly hel

[gem5-users] (no subject)

hi all.. I am trying to install gem5 am facing this error..have installed scons,swig,python.. kindly help me out scons: Reading SConscript files ... Error Don't know what compiler options to use for your compiler. compiler: None version: COMMAND NOT FOUND! If you're trying

Re: [gem5-users] (no subject)

I checked all the .py files within the src/mem/ruby folder... But i dont see any flaw in them (upto my knowledege)... I will try checking the cc files also... [Thank you for mentioning my mistake... i actually forgot and will see to it the subject is included always] On Sat, Feb 18, 2012 at 3:30

Re: [gem5-users] (no subject)

You should really put a subject on this so people who would be interested will see it when scanning through their mail. This sounds like a bug in one of the simulation scripts. I vaguely remember a recent change where there was a redundant copy of the system parameter being used with one of

[gem5-users] (no subject)

Hi... I am trying to run an ALPHA CMP simulation with two cores with ruby memory component When i try to run the simulation using "./build/ALPHA_FS/gem5.opt configs/example/ruby_fs.py -n 2 --l1i_size=16kB --l1d_size=16kB --l2_size=2MB --num-l2caches=1 --topology=Mesh --timing --script=runcsrip

[gem5-users] (no subject)

i've come up with some problem when runing gem5. after the compilation : it shows scons finished building target but when i enter the command it returns such an error: Traceback(most recent call last): File"",line1 , in AttributeError:'module'object has no attribute 'main' i did not manage to lo

Re: [gem5-users] (no subject)

; gem5 users mailing list Sent: Monday, December 12, 2011 12:46 PM Subject: Re: [gem5-users] (no subject) Sudhanshu, documentation on gem5 is available on our website www.gem5.org. -- Nilay On Mon, 12 Dec 2011, sudhanshu jha wrote: Hello, My name is Sudhanshu. I am using gem5 for simulations

Re: [gem5-users] (no subject)

. From: Nilay Vaish To: sudhanshu jha ; gem5 users mailing list Sent: Monday, December 12, 2011 12:46 PM Subject: Re: [gem5-users] (no subject) Sudhanshu, documentation on gem5 is available on our website www.gem5.org. -- Nilay On Mon, 12 Dec 2011, sudhanshu

Re: [gem5-users] (no subject)

Sudhanshu, documentation on gem5 is available on our website www.gem5.org. -- Nilay On Mon, 12 Dec 2011, sudhanshu jha wrote: Hello, My name is Sudhanshu. I am using gem5 for simulations.?Can you please let me know if there is a document that specifies the architecture of gem5, in terms o

[gem5-users] (no subject)

Hello, My name is Sudhanshu. I am using gem5 for simulations. Can you please let me know if there is a document that specifies the architecture of gem5, in terms of module and its working model (document of detailed software architecture of gem5 and its work flow)? I need to understand the work

[gem5-users] (no subject)

Hi, I have a general question in running multiple threads in multicore environment. In M5 simulation, if a core is assigned with multiple threads, does that core executes the threads one after another or the core uses some kind of round-robin policy/time-multiplexed way? Thanks, Dibakar Gope Texas