Dear sir srry for wrong interpretation..........please check again and correct me if i am wrong...........
my understanding................. If......physical address space ........1GB.................size of physical address 30-bits....... Now, 1. if size of on chip L2 cache is 4MB 2. block size.........64byte 3. 16 banks and 16 way set associative then physical address interpretation will be as follows -------------12bits for Tag--------------------8bits for index-----------------------4bits to select bank----------------------6 bits for block offset sir, please correct me if i am wrong.................. thanks On Sat, Nov 24, 2012 at 11:28 AM, megha gupta <megha122...@gmail.com> wrote: > my understanding...................physical address space .........means > on chip L2 cache > 1. if size of on chip L2 cache is 4MB > 2. block size.........64byte > 3. 16 banks and 16 way set associative > > then physical address is of 50 bits and its interpretation will be as > follows > > -------------32bits for Tag--------------------8bits for > index-----------------------4bits to select bank----------------------6 > bits for block offset > > > sir, please correct me if i am wrong.................. > -- Nitin Chaturvedi Lecturer, EEE/IU BITS, Pilani (Raj)
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