Your logic sounds correct to me for single core. For multi core, the last level cache is shared, and you can get block from other core’s L1 dcache. So you need to think through about what behavior you are expecting from your design and make changes or keep things same.
On Mon, May 13, 2019 at 12:02 AM Muhammad Avais <[email protected]> wrote: > Dear Abhishek, > > Many thanks for your reply. I will set the flag in response packet > for L2 hit. This flag will be default reset, therefore, I think I will not > need main memory flag in this case. > Please, let me know if you feel a problem in this logic. > For multicore simulation, what should be the difference? > > Many thanks for your response, > Best regards, > Avais > > On Sat, May 11, 2019 at 8:15 AM Abhishek Singh < > [email protected]> wrote: > >> What you do, is create flags in src/mem/packet.hh for various cache >> levels. >> Whenever you hit in L2, you can set the L2flag in response pkt. >> And if it is misses in L2, set main memory flag in response pkt, as you >> are sure you will get data from main memory. >> Here we are assuming it’s a single core simulation. >> >> On Fri, May 10, 2019 at 5:42 AM Muhammad Avais <[email protected]> >> wrote: >> >>> Dear All, >>> >>> 1- For blocks loaded in the L1 cache, how can I distinguish that it was >>> loaded into the L1 cache from the L2 cache (L2 hit) or main memory (L1 >>> cache)? >>> >>> Many thanks, >>> Best Regards, >>> Avais >>> _______________________________________________ >>> gem5-users mailing list >>> [email protected] >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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