Re: [gem5-users] Building linux for gem5

2015-01-23 Thread mohammad reza Soltaniyeh via gem5-users
Shu! Do it like this. git checkout v2.6.27 Regards, Reza On Sat, Jan 24, 2015 at 12:33 AM, Wei Shu via gem5-users < gem5-users@gem5.org> wrote: > Hi all, > > Am I the only one who confused at the command of updating linux-stable? > > Here is my command: > ~/linux-stable/.hg > git checkout 2.6

Re: [gem5-users] Building linux for gem5

2015-01-22 Thread mohammad reza Soltaniyeh via gem5-users
use 2.6.27 version. Can you > >>please > >> share how exactly you did it for X86 ISA ? Thank you! > >> > >> On Wed, Jan 21, 2015 at 6:08 PM, Amirali Boroumand > >> wrote: > >>> > >>> Hi Mohammad Reza, > >>> > >>>

Re: [gem5-users] Building linux for gem5

2015-01-21 Thread mohammad reza Soltaniyeh via gem5-users
Alpha ISA, but I've compiled linux kernel > (version 2.6.32.63) for x86 ISA, and it booted up smoothly. What linux > version did you try? > > - Amirali > > On Wed, Jan 21, 2015 at 9:33 AM, mohammad reza Soltaniyeh via gem5-users < > gem5-users@gem5.org> wrote: > >>

[gem5-users] Building linux for gem5

2015-01-21 Thread mohammad reza Soltaniyeh via gem5-users
Hello everyone, I have been following the instruction given http://www.m5sim.org/Linux_kernel to compile linux kernel for Alpha ISA. However, it seems that it is out dated. So, is there anyone who successfully compiled linux kernel and checked if gem5 can be run on top of it ? I was able to build

[gem5-users] Page table in FS mode for Alpha architecture

2015-01-14 Thread mohammad reza Soltaniyeh via gem5-users
Hi everyone! I am wondering how pages added to TLB in full system mode for ALPHA architecture. I know In SE mode, some struct were defined (named as ptable) that work as pagetable. However, the pagetable and TLB and how they really working together is really confusing in FS mode. I appreciate any

[gem5-users] [Slicc Code generation] peek keyword

2014-10-21 Thread mohammad reza Soltaniyeh via gem5-users
Dear All, I added one simple public variable to the RubyRequest class in RubyRequest.hh file; and I was trying to access that variable as a part of cache coherence protocol (MOESI_hammer-cache.sm). I know after using *'peek keyword *(like this: (mandatoryQueue_in, RubyRequest, block_on="LineAddr

Re: [gem5-users] Page Table in X86 Architecture

2014-10-07 Thread mohammad reza Soltaniyeh via gem5-users
port in SE mode for KVM, > which blurs the distinctions above, but that's not a typical use case at > this point.) > > Steve > > > On Tue, Oct 7, 2014 at 7:48 AM, mohammad reza Soltaniyeh via gem5-users < > gem5-users@gem5.org> wrote: > >> Dear All, >&g

[gem5-users] Page Table in X86 Architecture

2014-10-07 Thread mohammad reza Soltaniyeh via gem5-users
Dear All, I am working with X86 architecture in Gem5 and more specifically I am interested in Virtual address management in gem5. However, I have some difficulties in understanding the big picture of page table management in gem5. I divide them into three main modules. TLB, PageTable, and PageTabl