Dear All, I am working with X86 architecture in Gem5 and more specifically I am interested in Virtual address management in gem5. However, I have some difficulties in understanding the big picture of page table management in gem5. I divide them into three main modules. TLB, PageTable, and PageTableWalker. To put my question in perspective, I give an example.
When a memory request comes in, we first try to access TLB to check whether corresponding entry is available there or not! So, in which module we search withing the TLB. Actually, I don't know which data structures has been used for TLB. I just say List, Trie and even simple array in the codes but which one is really works as TLB?! This is my first question. Then, suppose we have a miss in TLB access. In this case, we should refer to the Page table to found possible entry there. Where we do so in gem5 ?! In other words, I can not find any structure which can play the role of pagetable in our architecture. There is no clear definition of page table in the codes.?! this is my second question. Putting it another way, where we check if access to the page table is miss or hit?! Then, in the case we have a page table fault, we should create a new page table entry and add it to both pagetable and TLB. I guess this should happen somewhere in pagetable_walker code. Can you please also exactly where i can find the codes for this part?! I hope my questions would be clear enough. I just want to get the whole idea of page table management in gem5 in order to apply some modification! Thank you in advance! Regards, boyrealmadred
_______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
