Andreas, you should really write a page on the traffic generator and its
capabilities.
--
Nilay
On Wed, 16 Jan 2013, Andreas Hansson wrote:
Hi Victor,
The TrafficGen module (in src/cpu/testers) supports trace replay. The trace
format is the same as what the gem5 CommMonitor produces, but yo
On Tue, 15 Jan 2013, Rx Ni wrote:
Hi, all,
I have met a problem shown as below:
gem5.opt: build/X86_MESI_CMP_directory/cpu/o3/fetch.hh:105: void
DefaultFetch::FetchTranslation::finish(Fault, RequestPtr,
ThreadContext*, BaseTLB::Mode) [with Impl = O3CPUImpl, Fault =
RefCountingPtr, RequestPtr =
On Mon, 14 Jan 2013, Jordan Fix wrote:
Hello,
I'm doing simulations with the Ruby memory system. I found a comment in
configs/ruby/MESI_CMP_directory.py that says:
"# Note: the L2 Cache latency is not currently used"
Is this comment old/no longer true? Or is the ruby memory system for
MESI_
On Tue, 15 Jan 2013, Ding, Hongyuan wrote:
Dear All,
I'm a beginner to gem5. Recently, I have compiled MEVBench for ARM
architecture, which should be used in FS mode since they were
dynamically compiled. I guess the output files of gem5 is generated when
I begin to load the linux system in g
On Mon, 14 Jan 2013, Yanqi Zhou wrote:
I used:
/gem5/build/ALPHA/gem5.opt --debug-flags=Exec,-ExecSymbol
--trace-start=2420065974500 --trace-file=/scratch/gpfs/yanqiz/%s_new.out
--outdir=m5out/%s configs/example/fs.py --caches --l1i_size=8kB --l1d_size=8kB
--cpu-type=detailed -I 20
-
On Sun, 13 Jan 2013, Bahar Asgari wrote:
Dear Naily;
Thank you very much for your help and kindly attention.
Now I have another question. this time I want to run multiprogrammed
workloads on a multi-core processor (whereas each processor core executes
one benchmark workload) in"se" mode. therefo
On Sun, 13 Jan 2013, Abu Saad wrote:
*Hi all
How I run the benchmark on gem5?*
You should read the documentation available on gem5.org.
--
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On Fri, 11 Jan 2013, Yiding Han wrote:
Thanks for the good work. After applying the patch the segfault is fixed.
The same message still pops up when gem5 exits after creating a checkpoint,
although it seems pretty harmless.
Ali had committed a patch a few days to fix the problem occurring at
On Thu, 10 Jan 2013, Nilay Vaish wrote:
Your trace was not of much help since it is not immediately clear as to what
pointer is being dereferenced incorrectly (one of the major causes of
segmentation faults). But I was able to reproduce the problem. The following
variable is invalid
On Fri, 11 Jan 2013, Mostafa Mahmoud Hassan wrote:
I could not figure out what is the problem in the first place. All what
I can see is that the code behavior seems illogical because it will
certainly cause the assertion to fail consistently in timing mode
If the code that you are claimin
On Thu, 10 Jan 2013, Yiding Han wrote:
Thanks for the reply:
gdb shows that the segfault is happening in decode_cache.hh:
Program received signal SIGSEGV, Segmentation fault.
getPage (this=0x2ff4ee0) at build/X86/cpu/decode_cache.hh:86
86if (recent[0] != pageMap.end()) {
Here is a bac
What all did you try to solve this issue? Your initial reasoning for the
problem was certainly incorrect.
--
Nilay
On Fri, 11 Jan 2013, Mostafa Mahmoud Hassan wrote:
Any guesses with this guys ?
Regards
--
why do you think that
On Thu, 10 Jan 2013, Yiding Han wrote:
Hi,
As a new user, I am running the latest version of gem5 on CentOS 6. I want
to simulate the SPEC2k6 benchmarks with a X86 architecture. I compiled
./build/X86/gem5.opt without any issue. The SPEC2k6 benchmarks are all
compiled with -static flags, which
On Wed, 9 Jan 2013, Zeng Lu wrote:
We are connecting 4 CMPs by a Hub chip through HT bus, each CMP has 16 cores
with 3 level cache hierarchy
CMP:
1. L1,L2 are private and L3 is shared, bit vector directory is maintained in
L3.
2. HT controller with cache coherence extension is able to connect an
On Tue, 8 Jan 2013, Musharaf Hussain wrote:
Hi all
I run one benchmark on gem5.opt with "--debug-help" flag. What are the meaning
of none others options. I added here my traceback.
The output you had posted were the debug-flags that are available in gem5.
You can read more about debug-flag
On Sun, 6 Jan 2013, Zeng Lu wrote:
Hi all,
I am trying to implement a two level directory hierarchical cache
coherence Numa(ccNuma) system using Gem5. But I have no idea yet. Is
there any way to do it?
Thanks.
It is possible to create a cc-NUMA system. If you talk more specifically
about wha
On Tue, 8 Jan 2013, Hui Zhao wrote:
Hello
Can I run Gem5 with x86 in FS mode with SMT support? (or is this
function available in Gem5 now?)
It is highly unlikely that SMT works correctly with x86 architecture in
FS mode. I would suggest that you try out things in the SE mode. You
probably wi
This changeset adds code to configs/common/Simulation.py which tries to
access a variable before it has been assigned any value.
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On Tue, 8 Jan 2013, Mostafa Mahmoud Hassan wrote:
I found that the kernel gets these values in this function (exists in
linux-2.6.28.4/arch/x86/kernel/cpu/common.c):
void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
{
unsigned int n, dummy, ebx, ecx, edx, l2size;
n = c->extende
On Tue, 8 Jan 2013, Andreas Hansson wrote:
If you've installed protoc using apt/yast etc pkg-config should know how
to use it.
I just compiled the source and installed it in a non-standard location.
protoc is available in the path and the libraries are available in
LIBRARY_PATH.
Can you
On Tue, 8 Jan 2013, Andreas Hansson wrote:
Hi Nilay,
I am not sure I follow your comment. pkg-config is used for protobuf, but
not for anything else at this point. I cannot reproduce the error on my
side as my pkg-config knows of protobuf and handles it correctly. The
tests in the scons script
On Mon, 7 Jan 2013, Mostafa Mahmoud Hassan wrote:
No, the kernel is not missing anything. Download the source of the Linux
kernel and try to figure out how the information about caches is fetched
from the processor. Note that you do know the format in which the
kernel displays cache info dur
On Mon, 7 Jan 2013, Jinchun Kim wrote:
It's X86 FS and classic model.
Jinchun Kim
On Jan 7, 2013, at 4:17 PM, Nilay Vaish wrote:
On Mon, 7 Jan 2013, Jinchun Kim wrote:
I was printing out TLB entries whenever virtual address hit or miss on TLB.
And I found that TLB miss occurs even t
On Mon, 7 Jan 2013, Ali Saidi wrote:
Hi Nilay,
Do you have protoc installed, but pkg-config doesn't
know about it?
Yes, but it should not matter. I would expect that protoc and the
associated libraries are detected like gcc.
--
Nilay
___
gem5-
This changeset adds support for building with google protobuf. I think the
patch erroneously assumes that pkg-config will work correctly in all
situations. I got the following error while trying to build gem5 --
scons: Reading SConscript files ...
Package protobuf was not found in the pkg-confi
On Mon, 7 Jan 2013, Jinchun Kim wrote:
I was printing out TLB entries whenever virtual address hit or miss on TLB.
And I found that TLB miss occurs even though TLB already has matched entry
in it.
For example,
4949665272500: system.cpu.dtb: L1 TLB Miss : VA = 0x7fab3f32c280
4949665272500: syste
On Mon, 7 Jan 2013, Steve Reinhardt wrote:
I'm even further behind than Andreas, but I'm curious about the situation
here. It's been a while, but last time I checked, compiling the x86
decoder with gcc took about 1GB of RAM (definitely <1.5GB). If something
has happened to the code and/or gcc
On Mon, 7 Jan 2013, Mostafa Mahmoud Hassan wrote:
So how does the linux kernel generates the info present in this file?
I am afraid that I do not have that much experience with Kernels, but do
you mean that the compiled kernel I am using is missing something? I am
using the one found on
On Mon, 7 Jan 2013, Mostafa Mahmoud Hassan wrote:
I guess it is supposed that the "configs/common/CacheConfig.py" should
set these parameters for the processor at the first place, right ??
On the other hand, such info exists on the following path (for my host
machine) :
/sys/devices/system/
On Fri, 4 Jan 2013, mehmet basaran wrote:
Hi all,
This is probably a dumn question but what should I do before instantiating
m5? I was going over tutorials, and tried to create a simple simulation
script. The error message I have is;
On Mon, 31 Dec 2012, Mostafa Mahmoud Hassan wrote:
Dear All,
I am trying to run GEM5 FS mode for X86 ISA with ruby. I am using this command
./build/X86_MESI_CMP_directory/gem5.opt -d
/home/mostafa/GEM5/temp_sim_results/16P_FBV_x86_fft
./configs/example/ruby_fs.py --cpu-type=timing -n 4
On Thu, 3 Jan 2013, zhengchl wrote:
Hi,
When I used ruby cache coherence protocol MOESI_CMP_directory, I found that
when a replacement taking place, the protocol allocated a TBE entryand made
use of TBE entry instead of cache entry to complete a Replacement transition.
So, it looks like a re
On Mon, 31 Dec 2012, Nilay Vaish wrote:
On Mon, 31 Dec 2012, Mostafa Mahmoud Hassan wrote:
Hi Nilay
1) I tried increasing the memory in FSConfig to 2047MB 2) I tried to use
timing simple CPU instead of detailed 3) I tried to decrease the number of
objects (number of L2 Cache banks
On Mon, 31 Dec 2012, Mostafa Mahmoud Hassan wrote:
Hi Nilay
1) I tried increasing the memory in FSConfig to 2047MB 2) I tried to use
timing simple CPU instead of detailed 3) I tried to decrease the number
of objects (number of L2 Cache banks, number of directories) hoping that
the simu
On Thu, 27 Dec 2012, ali bagherian wrote:
Hi,
I tried to compile Gem5. but I got following error:
scons: Building targets ...
[ CXX] X86/arch/x86/generated/decoder.cc -> .o
virtual memory exhausted: Cannot allocate memory
scons: *** [build/X86/arch/x86/generated/decoder.o] Error 1
scons:
On Fri, 21 Dec 2012, Xin Tong wrote:
Hi
Does gem5 implement a TLB for x86 O3 processor ?
Yes.
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On Thu, 20 Dec 2012, Jordan Fix wrote:
There have been modifications to the memory system, however it doesn't
make sense to me that it would work on one machine and not the other. Is
the gem5 port system interfacing with the kernel from the machine it's
running on or something? Why would it wo
On Thu, 20 Dec 2012, Jordan Fix wrote:
Not sure if you mean the physical memory of the simulator or the machines
they're running on.
The simulator is running with 512Mb.
The machine which works has 12Gb, and the machine which doesn't has 8Gb.
On Dec 20, 2012, at 9:25 PM, Nilay V
On Thu, 20 Dec 2012, Jordan Fix wrote:
Hello,
I'm trying to run some full system ruby simulations with multiple cores.
I can start the simulation with 2 cores, but I've tried 4 and 8 and I
get the attached error message. I've looked this issue up a little bit
and it seems that this should on
On Tue, 18 Dec 2012, Muhammad Shoaib bin altaf wrote:
Hey List,
I am running Full system X86 and the bigger picture is to integrate
accelerators (or co-processors) in gem5. I think starting with adding devices
will be a good starting point.
I have added a device "Hello device" in the system
On Wed, 19 Dec 2012, Arthur Perais wrote:
Hi all,
Correct me if I am wrong, but as I understand the code, for a store
instruction, the D-Cache is only accessed when the store writes back, that is
when it is at the head of the LSQ and has been committed and a port is
available.
Now, if there
don't think dumping
and resetting ruby statistics has been done by 'dumpreststats'.
On 12/16/2012 11:33 PM, Nilay Vaish wrote:
On Sun, 16 Dec 2012, zhengchl wrote:
Hi,
I want to call function 'Profiler::printStats' of Ruby when
'dumpresetstats' is executed. So I tra
On Sun, 16 Dec 2012, hanfeng QIN wrote:
I am sorry for that we have diverse opinions. I think firstly you should
refer to this paper to understand the simulation methodology I mentioned.
I don't think you have any opinion. If you had one, you would clearly
stated why you believe the experim
On Sun, 16 Dec 2012, zhengchl wrote:
Hi,
I want to call function 'Profiler::printStats' of Ruby when 'dumpresetstats'
is executed. So I track the the call stack of dumpresetstats.
I guess you are bent on doing something that already exists.
--
Nilay
___
On Sun, 16 Dec 2012, pmo...@masonlive.gmu.edu wrote:
Thank you Nilay.
I don't know where to change the parameters so it will look for console in the
path I have put it in and not the default. I spent all day looking in different
files and change parameters and I still get the same error. I l
Andreas, can you add a page on the traffic generator to the Wiki?
Thanks
Nilay
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On Sat, 15 Dec 2012, pmo...@masonlive.gmu.edu wrote:
Hello,
I am running FFT on Alpha based on the tutorial. I have changed the FSConfig :
path = env['/home/pm/gem5-stable/full_system_images/disks'].split(':') in
SysPaths. And in Benchmarks: return env.get('LINUX_IMAGE',
disk('linuxparsec-2-
On Thu, 13 Dec 2012, sarde...@uci.edu wrote:
Hi Nilay,
Yes, I had to make two changes to make it compile.
1. Solaris does not recognize std::isnan() function. So I had to put my
own implementation. This was a solution posted online >
https://gist.github.com/870503
-namespace std
-{
- int isnan
On Fri, 14 Dec 2012, zhengchl wrote:
Hi,
As we all know, we can get simulation statistics of a interested region by
using Gem5 utility 'dumpresetstats', but these statistics are only about cpu
and lack of ruby cache information. And ruby simulation output file
'ruby.stat' is about the entire
On Fri, 14 Dec 2012, hanfeng QIN wrote:
I know the options '-F' and '-W'. Actualy, I use them together with '-I'
option to specify the detailed instruction numbers (as denoted with N3 in my
previous mail). It seems that the default implementation in
configs/common/Simulation.py will pass the N
On Thu, 13 Dec 2012, sarde...@uci.edu wrote:
Hi,
Has anyone been able to run gem5 on Solaris? I am using Solaris 2.11 with
64 bit Sparc Architecture. Gem5 website also does not explicitly mention
that it runs on Solaris.
I was able to compile X86/gem5.debug on Solaris. But i get a Bus
Error(Co
On Wed, 12 Dec 2012, hanfeng QIN wrote:
Hi all,
I learn a common multi-programmed simulation methodology adopted by many
architecture researchers. But I am not clear its implementation internals. I
describe its idea in brief as following.
For multi-programmed workload consists of M programs
On Wed, 12 Dec 2012, 刘宇航 wrote:
Hi all,
Under FS mode while using Ruby, I run the splash benchmark using the
pre-compiled v1-spalsh-alpha.tgz from http://gem5.org/Download, but encounter
the following error:
modprobe: FATAL: Could not load /lib/modules/2.6.27.6-dirty/modules.dep: No
such fi
On Thu, 13 Dec 2012, Yongbing Huang wrote:
Hi all,
I set the associative of L2 cache to 16 in the configuration file
when booting ARM FS simulator. However, the boot log of gem5 shown below
indicates that the l2 cache is 8-way. I wonder whether the boot information
is not correct or t
On Sat, 8 Dec 2012, Udayan Umapathi wrote:
Hello All,
I am trying to add a custom state to "MESI_CMP_directory-L1cache.sm. I added
statement a new cache state similar to ,
transition(M,L1_Replacement, M_I,){
forward_eviction_to_cpu
}
for debug purpose. The code does not seem to compile with
On Fri, 7 Dec 2012, Jinchun Kim wrote:
Hi, All.
I was wondering if anyone can make a quick check for L2cache misses in ruby.
It seems like the number of L2cache access and miss doesn't show proper
numbers.
In my simulation, L2cache miss is the exactly same number of L1Dcache miss
+ L2Icache miss
On Fri, 7 Dec 2012, Anouk wrote:
Hi Nilay,
Thanks for your answer.
I am changing my response. Depending on the protocol, there are operations
that are carried out which might be termed as re-ordering. For example, a
controller may block all messages while it is waiting for a particular
me
On Fri, 7 Dec 2012, Anouk wrote:
Hi,
I have a question regarding message ordering in Ruby.
Because the SimpleNetwork offers adaptive routing, in which messages can proceed
in the network out-of-order, I always assumed some kind of re-ordering was in
place.However, I made some changes to the net
On Thu, 6 Dec 2012, Abhishek Deshpande wrote:
Hi,
I am new to Gem5.
Please let me know how to enable L3 and confirm that it is working. I am
using ALPHA architecture available in gem5 without any modification and
using se.py configuration file as available.
Since you have not made any changes
On Thu, 6 Dec 2012, Abhishek Deshpande wrote:
Hello,
I am trying to find trace for Last Level Cache or L3, as I want to find
Read and Writes Hits, Misses to LLC/L3.
Using my current argument, I am able to find trace log for L1 and L2
cache. But, though I have L3 cache sizes defined, I am not g
On Wed, 5 Dec 2012, Udayan Umapathi wrote:
Hello All,
I have successfully modified the gem5 Ruby Cache Memory model suit my
needs. At run-time, the benchmark I run terminates due to a invalid
state transition. I have a trace of the transitions that I have got
through the debug flag "Protocol
On Mon, 3 Dec 2012, Udayan Umapathi wrote:
Hello All,
The query I have is related to the Ruby memory model. I modified the existing
Cache memory model(../Ruby/System/CacheMemory.cc). I wanted to know if I have
to specify the cache size and associativity and similar parameters throughout
comm
On Tue, 4 Dec 2012, vinh ngo wrote:
I am very new to GEM5.
I have tried so much to generate the ruby.stats file but no result.
I also kept searching in gem5 users archives but no solution.
Can you please give me a command line that can generate the ruby.stats file.
My command is:
build/MIPS/ge
On Mon, 3 Dec 2012, Jordan Fix wrote:
Hello,
I'm attempting to make some modifications to the Ruby memory system and the
MESI directory protocol. I was wondering if anyone could give me an overview of
what happens when for example a load occurs -- how the system interacts to
check/update MES
On Sun, 2 Dec 2012, Anusha wrote:
I am not to find the place where this LLSC flag is actually set. (I
wasn't able to find any code that used SetFlags(LLSC)). Am I missing
something here?
Of course! You are missing the power of grep.
--
Nilay
___
ge
On Sun, 2 Dec 2012, Udayan Umapathi wrote:
Hello,
I am trying to modify the existing Cache model in Gem5. I figured that,
\ruby\System\Cache_memory.cc has the definition for the cache memory
model. There is a 2d array, "m_cache" of size
(cache_number_of_sets*associativity). There is "m_tag_i
On Sun, 2 Dec 2012, Tianyun Zhang wrote:
Hi all,
I ran the benchmarks by full system mode. The benchmarks did run but
they exit with an exception:
hack: be nice to actually delete the event here
Exiting @ tick 5766801110500 because m5_exit instruction encountered
terminate called after thro
On Sat, 1 Dec 2012, leonardo wrote:
Hello everyone
Is there any chance that I could use Ruby without any cache coherence protocols?
What should i do?
Thanks.
Does not seem possible to me. You can use the classic memory system, if it
serves your purpose.
--
Nilay
___
On Fri, 30 Nov 2012, hanfeng QIN wrote:
I apologize for my carelessness, Nilay. I am sorry to say that I still can
not prevent the error even I revert the patch. To make you understand my
simulation flow, I list my process as following.
Step 1: I made a checkpoint using TimingSimple CPU type.
On Fri, 30 Nov 2012, hanfeng QIN wrote:
On 11/29/2012 01:07 AM, Nilay Vaish wrote:
On Wed, 28 Nov 2012, hanfeng QIN wrote:
I used mercurial to clone the latest version of gem5 in development
repository. By the way, I used to work on the stable release, however,
when I was trapped in a
On Thu, 29 Nov 2012, Sumit Dhoble wrote:
According to the document, there is an M5 pseudo instruction inside
the benchmark that causes the checkpoint to be created.
You are correct. The segmentation fault is reached before that pseudo
instruction is reached. The cause of segmentation fault is gl
On Thu, 29 Nov 2012, Sumit Dhoble wrote:
Contents of the auto-generated script :
#!/bin/sh
# File to run the bodytrack benchmark
cd /parsec/install/bin.ckpts
/sbin/m5 dumpstats
/sbin/m5 resetstats
./bodytrack /parsec/install/inputs/bodytrack/sequenceB_1 4 1 1000 5 0 3
echo "Done :D"
/sbin/m5
On Wed, 28 Nov 2012, Sumit Dhoble wrote:
Hi all,
I am a beginner with Gem5. I need to run PARSEC benchmarks on ALPHA. I
followed instructions from the document provided by UT Austin.
In order to follow the document completely, I'm using an older version
of Gem5 (http://repo.gem5.org/gem5/archi
On Wed, 28 Nov 2012, Jordan Fix wrote:
Hello,
I had a question about the transition function in SLICC. The
documentation shows an example "transition(IM, Data, M)" and says that
"The initial state is IM. If an event of type Data occurs in that state,
then final state would be M."
Then ther
On Wed, 28 Nov 2012, Roberto Rodríguez-Rodríguez wrote:
Hello everyone,
I have a doubt, in the file MOESI_CMP_directory-L1cache.sm the LRU queue
state, I think, is never updated.
The actualization of the LRU queue is done by the "touch" method of the
replacement policy class (src/mem/ruby/sys
On Wed, 28 Nov 2012, hanfeng QIN wrote:
I used mercurial to clone the latest version of gem5 in development
repository. By the way, I used to work on the stable release, however, when
I was trapped in a coherence protocol error then I switched to the
development repository to work around that
On Tue, 27 Nov 2012, hanfeng QIN wrote:
Hi all,
I adopt gem5 in SE plus Ruby mode. I want to warm up cache before data
measurement. During my experiment, I found the '-W' option does not work. The
simulation process is controlled in Ruby mode from scratch instead of after
instructions as ex
On Tue, 27 Nov 2012, Tianyun Zhang wrote:
Thanks. I read it, but it seems like I need to know the exact tick time
when the system finishes booting and then set the trace-time flag. But it's
hard to know the tick time because every time it is different.
Thanks again
I would expect the system t
On Mon, 26 Nov 2012, Tianyun Zhang wrote:
Hi,
I added a new debug flag to print some debug info. I run under full
system mode, but I find that my debug info is printed out as soon as the
system starts to boot. How can I control the debug info to be printed out
after my benchmark starts to ru
On Mon, 26 Nov 2012, Roberto Rodríguez-Rodríguez wrote:
Hello everyone,
I need to create a model with cpus, L1i, L1d and L2 private and shared L3.
As example I am using the file configs/ruby/MOESI_CMP_directory.py, these
file depends of src/mem/protocol/(MOESI_CMP_directory-dir.sm,
MOESI_CMP_di
On Mon, 26 Nov 2012, zhengchl wrote:
Hi,
in MOESI_CMP_directory-dir.sm line 407, when dir in M or O state receive
DMA_WRITE, the dir controller should send DMA_WRITE request to cache in order
to get latest data. As the follow code does:
1.action(f_forwardRequestDirIsRequestor, "\f", des
On Sun, 25 Nov 2012, Pavlos Maniotis wrote:
On Sun, 2012-11-25 at 08:29 -0600, Nilay Vaish wrote:
This violates coherence since more than one processor can assume that they
have write permissions to the same block.
--
Nilay
If it violates data coherence, how is it explained that the
On Sun, 25 Nov 2012, Pavlos Maniotis wrote:
In /gem5/configs/ruby/MOESI_CMP_directory.py I changed this code:
by this way I connect each cpu's ports to the same sequencer created in
MOESI_CMP_derectory.py and I have used ALPSA ISA.
I am not convinced that the simulator works correctly withou
On Sun, 25 Nov 2012, Pavlos Maniotis wrote:
For anyone who would like to share one L1 cache among multiple cpus I
have found a possible solution that seems to work:
1) I modified the ruby protocol specific python config file (for example
MOESI_CMP_direcory.py in /gem5/configs/ruby) to create ju
On Sat, 24 Nov 2012, pushkar nandkar wrote:
Hi,
Currently the classic memory system has a non-blocking cache which is
handled using MSHR and Write Buffer.
I want to implement a blocking cache and measure time/clock ticks for which
the CPU stalled. I am implementing a multicore system here.
Is
On Sat, 24 Nov 2012, pushkar nandkar wrote:
Nilay,
If you are using the same se.py that comes with the gem5, if there is only
one workload specified, All the system.cpu[i].workload is assigned the same
process.
However if I use the same se.py specifying the -c
"splash2/codes/kernels/radix/RADI
On Sat, 24 Nov 2012, zhengchl wrote:
Hi,
I implement a 1 level cache coherence protocol based on MOESI-CMP-directory,
and my protocol passes Ruby_random_test with max 16 cores and 1000 loads.
But I'm not sure those testes are enough, what should I do next to verify a
protocol?
You ca
On Sat, 24 Nov 2012, pushkar nandkar wrote:
Hi,
I am new to Gem5.
I am trying to implement a system in the SE mode. The system has 4 inorder
cpus. I have downloaded the Splash2 benchmarks and using those binaries.
I am using the se.py right now.
Here is the command line
./build/ALPHA/gem5.op
On Sat, 24 Nov 2012, Frank Yang wrote:
Hi All,
I am trying to dig into Gem5 but I found it's fairly complicated. Can
someone give me any hint on how gem5 bring the concept of timing into
those CPU models? I can understand that each instruction is divided into
several stages, but how is the m
On Thu, 22 Nov 2012, Albert wrote:
It does make sense to include ports into the tlbs to communicate between them
if I want to model the message passing? Or it would be a better approach to
use the ports on the CPUs?
It is your design, you can decide what is possible!
I understood that the
On Sat, 24 Nov 2012, megha gupta wrote:
Dear friends
i am a new gem5 users and a beginnertherefore alot of
queries...
1. In a CMP.the address request send through a
coreis a virtual address( as per theory) and TLB convert it
into physical address..
On Fri, 23 Nov 2012, Jordan Fix wrote:
Hello all,
I'm attempting to modify the MESI_CMP_directory cache coherence
protocol. I was wondering if there is an easy way to write some simple
memory operations and and view the resulting way the state machine and
network respond, other than inspecti
On Wed, 21 Nov 2012, Pavlos Maniotis wrote:
Hello everyone,
I am trying to simulate a system with 4 cpus and
one shared L1 cache (cache shared among cpus).
I tried to modify MESI_CMP_directory.py in
/gem5/configs/ruby by changing this code:
(I actually removed the "for" command and replaced i w
On Tue, 20 Nov 2012, Silky Arora wrote:
Hi,
I am trying to create a Non-Uniform Cache Access in gem5 for adaptive cache
spilling.
I was wondering if this achieves the purpose
./build/ALPHA_MESI_CMP_directory/gem5.opt configs/example/ruby_mem_test.py
--num-cpus=16 --num-dirs=4 --num-l2caches=16
On Tue, 20 Nov 2012, Roberto Rodríguez-Rodríguez wrote:
Hello everybody,
Is there a Ruby launcher example similar to se.py, there is a ruby_fs.py
equivalent to fs.py. I don`t know if it is possible to run a single execution
with Ruby model.
What do you mean by single execution?
--
Nilay
On Mon, 19 Nov 2012, Jinchun Kim wrote:
Hi, All!
I was trying to run x264 & ferret on X86 gem5.
Compiling and running on my host machine works totally fine.
However, when I try it on gem5, I had to boot with 16 CPU and do simulation
with 16 threads.
Unless it shows segmentation fault error.
(Ot
On Mon, 19 Nov 2012, Roberto Rodríguez-Rodríguez wrote:
Hi, I have problems changing the replacement policy to be used by the
simulator. I just want to change the LLC policy.
I saw the options for se.py: "./build/X86/gem5.opt configs/example/se.py
-h" but there is not an option for the replacem
On Tue, 20 Nov 2012, Jordan Fix wrote:
Hello,
I'm trying to run an application which uses mmap. It runs fine on my native x86
machine. However when I run it on gem5 it seems mmap is failing:
REAL SIMULATION
info: Entering event queue @ 0. Starting simulation...
warn: instruction 'f
On Tue, 20 Nov 2012, Tianyun Zhang wrote:
Hi,
I use the gem5-stable-b9ba22cb23f2 version.
And here is what I got from gdb backtrace. Is it helpful?
You are using a 17 month old version of gem5. I suggest that you update to
something recent.
--
Nilay
On Tue, 20 Nov 2012, Tianyun Zhang wrote:
Hi,
I was stuck by some serious error when running ruby. I configured the
CPU Model to SimpleTimingCPU and source the MESI_CMP_directory.py file. I
didn't use any checkpoints
This error happens after the system finishes loading the running script but
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