On Thu, 22 Nov 2012, Albert wrote:
It does make sense to include ports into the tlbs to communicate between them if I want to model the message passing? Or it would be a better approach to use the ports on the CPUs?
It is your design, you can decide what is possible!
I understood that the ports are there to communicate MemObjects with the memory through the (network? a bus?), but TLBs are not MemObjects, the pageWalker is (because it have to access the memory to do the walk). So it won't make sense to include those ports in the TLB?
gem5 is a piece of software. It is possible to modify it so that a TLB has ports that connect it to other TLBs.
How CPUs communicate each other? I'm not really asking for an explanation, but to see if someone can point out where to look in the code. I'm using the arm_detailed processor.
Through the memory space that they are sharing. -- Nilay _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
