On Mon, 7 Jan 2013, Jinchun Kim wrote:
It's X86 FS and classic model.
Jinchun Kim
On Jan 7, 2013, at 4:17 PM, Nilay Vaish <[email protected]> wrote:
On Mon, 7 Jan 2013, Jinchun Kim wrote:
I was printing out TLB entries whenever virtual address hit or miss on TLB.
And I found that TLB miss occurs even though TLB already has matched entry
in it.
For example,
4949665272500: system.cpu.dtb: L1 TLB Miss : VA = 0x7fab3f32c280
4949665272500: system.cpu.dtb: tlb[41] : VPN = 0x7fab3f32c000, PPN =
0x1facd000
Translation for VA = 0x7fab3f32c280 is already in tlb[41].
However, it is considered as miss.
After this weird TLB miss, gem5 puts same translation in TLB again.
Are you sure that this entry that you printed is valid?
--
Nilay
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
