Re: [gem5-users] ARMv8 Client-Server configuration

2014-10-07 Thread Ivan Stalev via gem5-users
Hi Ali and Andreas, Is armv8 client-server supposed to work with detailed CPUs? Everything works with atomic CPUs for me, but when I restore from a checkpoint after boot with a detailed CPU, no progress is made. Thanks, Ivan On Mon, Sep 22, 2014 at 11:36 PM, Ivan Stalev wrote: > Hi Ali, > > I

Re: [gem5-users] Page Table in X86 Architecture

2014-10-07 Thread Steve Reinhardt via gem5-users
Yes, in FS mode the OS is the only thing that manages the page tables. Just like a real system. On Tue, Oct 7, 2014 at 9:28 AM, mohammad reza Soltaniyeh < m.soltani...@gmail.com> wrote: > I am talking about FS mode. I couldn't get the point about page-table > walker used in gem5. Is it bulky at t

[gem5-users] USE OF GEM5 IN FAULT TOLERANT issues

2014-10-07 Thread babak aghaei via gem5-users
HiI pray the Happiness and health full  life for everybody.. I am studying about the fault tolerant challenges of an interconnection network. I want know if take place studies about fault injection techniques used in GEM5 simulator.THANK YOU Best -

Re: [gem5-users] Modelling Cortex Arm7 architecture

2014-10-07 Thread Andreas Hansson via gem5-users
Hi Naveed, The InOrder CPU is deprecated. Have a look at Minor in src/cpu/minor. Andreas On 07/10/2014 17:23, "Naveed Ul Mustafa via gem5-users" wrote: > >Hi All, > >I need to model Cortex A7 architecture using gem5. It is a 8 >stage-pipeline architecture with in-order execution. > >Is there a

Re: [gem5-users] Page Table in X86 Architecture

2014-10-07 Thread mohammad reza Soltaniyeh via gem5-users
I am talking about FS mode. I couldn't get the point about page-table walker used in gem5. Is it bulky at the moment ?! In other words, OS is the only page table manager in FS mode.?! I've seen you add PageTableEntry to the new released code! But I could not guess what is the reason behind that.

[gem5-users] Modelling Cortex Arm7 architecture

2014-10-07 Thread Naveed Ul Mustafa via gem5-users
Hi All, I need to model Cortex A7 architecture using gem5. It is a 8 stage-pipeline architecture with in-order execution. Is there anyone who has worked on this or can anyone guide me where to start. I know there is InOrderCPU.py in src/cpu/inorder. In documentation it states that by default it

Re: [gem5-users] Read traces generated by CommMonitor

2014-10-07 Thread Andreas Hansson via gem5-users
I would suggest to have a look at: https://developers.google.com/protocol-buffers/ Andreas On 07/10/2014 14:25, "senni sophiane" wrote: >Hi Andreas, > >I just want to get cache bandwidth values to see how it changes over >time. For instance, I want to get for both reads and writes the >bandwidt

Re: [gem5-users] Page Table in X86 Architecture

2014-10-07 Thread Steve Reinhardt via gem5-users
Are you talking about SE or FS mode? In SE mode, typically the ISA-independent PageTable class is used to hold the page tables, and no walker is needed. In FS mode, the page tables are constructed in the simulated physical memory by the OS running on the simulated platform; we use the page-table

[gem5-users] Page Table in X86 Architecture

2014-10-07 Thread mohammad reza Soltaniyeh via gem5-users
Dear All, I am working with X86 architecture in Gem5 and more specifically I am interested in Virtual address management in gem5. However, I have some difficulties in understanding the big picture of page table management in gem5. I divide them into three main modules. TLB, PageTable, and PageTabl

Re: [gem5-users] MMAP a file in SE mode

2014-10-07 Thread Steve Reinhardt via gem5-users
We have a patch internally that implements more of mmap(), but unfortunately it's not quite ready to post. If you just want to do a read mapping (you don't care if writes to the mmap'd region get written back to disk), and you don't mind just reading the whole mmap region in up front (which you ne

Re: [gem5-users] Read traces generated by CommMonitor

2014-10-07 Thread senni sophiane via gem5-users
If I can extract the number of bytes per ms for reads and the number of bytes per ms for writes, for all the execution time. It will be great. Cordialement / Best Regards SENNI Sophiane Ph.D. candidate - Microelectronics LIRMM - www.lirmm.fr Le 07/10/2014 15:25, senni sophiane a écrit : > Hi And

Re: [gem5-users] Read traces generated by CommMonitor

2014-10-07 Thread senni sophiane via gem5-users
Hi Andreas, I just want to get cache bandwidth values to see how it changes over time. For instance, I want to get for both reads and writes the bandwidth value every ms from the beginning to the end of the execution time. But I need to know how are exactly the protobuf messages to extract correct

[gem5-users] MMAP a file in SE mode

2014-10-07 Thread Ahmad Hassan via gem5-users
Hi, The existing implementation in GEM5 SE mode only supports MMAP to /dev/zero. Has anyone implemented MMAP in gem5 that can map a file from the disk? If not, how can I extend this? Regards, ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.

Re: [gem5-users] Read traces generated by CommMonitor

2014-10-07 Thread Andreas Hansson via gem5-users
Hi Sophiane, What is it you want to do with the trace? I would suggest to implement what ever it is you want to do in C++ or Python and operate directly on the Protobuf Messages in the trace. Andreas On 07/10/2014 14:06, "senni sophiane via gem5-users" wrote: >Hi all, > >I managed to instantia

[gem5-users] Read traces generated by CommMonitor

2014-10-07 Thread senni sophiane via gem5-users
Hi all, I managed to instantiate a CommMonitor between tol2bus and L2 cache modifying the CachesConfig.py as follows : system.L2monitor = CommMonitor(trace_file = "L2_trace_tr.tr") system.tol2bus.master = system.L2monitor.slave #system.l2.cpu_side = system.tol2bus.master system.l2.cpu_side = syst