Ali,
Based on the stats I get for the entire ROI (non-periodic) of a benchmark, I
know approximately at which tick ROI starts and at which tick the ROI ends,
however I do not know how I can use this information for PERIODIC dumping of
stats for ROI only.
I am using statDump(period) which has
How do you know the simulator is in the ROI?
Provided you know when it will be in the ROI, you can can periodically dump the
stats at that point.
Ali
On Oct 24, 2012, at 1:07 AM, shervin hajiamini wrote:
>
> Hello Fernando,
>
> Thanks for the link.
>
> It seems that for getting the periodi
Hello Fernando,
Thanks for the link.
It seems that for getting the periodic stats of a benchmark I need to change
the source code of the benchmark, however I am wondering whether there is a way
to dump the stats ONLY for ROI periodically (w/o checkpoints) without modifying
the source code of
Ah, I see. Sorry, I misunderstood that point.
On Tue, Oct 23, 2012 at 7:48 PM, Steve Reinhardt wrote:
> Just a clarification on Paul's second point: the issue described in the
> email he's linked to strictly refers to backpressure for TLB misses (i.e.,
> pagetable walks). There definitely is ba
Hi All,
I meet a problem when I use the option of "--at-instruction"
I want to start to insert checkpoints at the 1000th instruction and after that
insert a checkpoint for each 1000 instructions.
The command is
./build/ALPHA_FS/m5.opt ./configs/example/fs.py -n1
--script=writescripts/blacksc
Just a clarification on Paul's second point: the issue described in the
email he's linked to strictly refers to backpressure for TLB misses (i.e.,
pagetable walks). There definitely is backpressure on the CPU for regular
memory accesses.
Steve
On Tue, Oct 23, 2012 at 12:49 PM, Paul Rosenfeld wro
Hi,
I added a function in CacheMemory.* called hashCompare(DataBlock dbk). This
function is called in MESI_CMP_directory-L2cache.sm:
-
in_port(responseIntraChipL2Network_in, ResponseMsg, responseToL2Cache, rank
= 1) {
..
if(in_msg.Type == CoherenceResponseType:MEMOR
As someone who has used (and tried to modify) both marssx86 and gem5, I
would like to add one (potential) benefit to the marssx86 side of things:
the emulation mode (via QEMU) allows you to boot the system very quickly up
to a region of interest and take a checkpoint right before the simulation
lau
Gem5 is almost fully deterministic in SE mode. I only know of one
exception (load linked/store conditional instruction pairs) and that is
being fixed. The committed instruction sequence should be the same every
time. I'd think you'd have to save the outcomes of all branches.
It might be easier
Hi, all,
I am trying to run ALPHA_FS+ruby+o3cpu+PARSEC, and I just find out that
there is a problem said "functionalWrite not Implemented". I tried to run
with ruby_random_test.py and it can work. I don't know what is the
difference between ruby_fs.py and ruby_random_test.py. My command:
./build/
On Mon, 22 Oct 2012, Runjie Zhang wrote:
Greetings,
I tried to write stressmarks in X86 assembly so that the simulated IPC or
O3CPU can hit N for a N-way out-of-order core. However, no matter how I
modify the assembly, the IPC could never reach 4 for a 4-way OoO core.
According to the execut
Thanks for your answer. Ruby is a module in GEM5 which simulate memory
hierarchy. Suppose there is an application that its execution time is 20 ms
on a real system. GEM5 simulate the application in about 15 min. Hos is
MARSS86 simulation speed?
On Tue, Oct 23, 2012 at 5:27 PM, Payne, Benjamin wro
Hello,
I'm not familiar with what you are referring to by the ruby module - is that an
addon for Gem5?
You have a good question, but how would I quantify the difference in simulation
speeds between MARSS and Gem5? Is there an established benchmark to run?
Kindly,
Ben Payne
From: gem5-users-
Hi Andreas,
I have tried to do that, but then I run in an other problem: the root
section in my checkpoints is empty, so there is no isa option and the
script crashes in the from_0 function. So I think the whole section has
to be filled before processing the file.
Unfortunately, I don't know h
Hi Nathanaël,
I am temtped to say, add it manually. We could always tweak the
cpt_upgrade.py script to assume 0 in the case of no version number being
present (feel free to post a patch :).
Andreas
On 23/10/2012 14:26, "Nathanaël Prémillieu"
wrote:
>Hi all,
>
>Since a long time ago, I have thi
I have a question about MARSS. As you know GEM5 simulation speed with ruby
module is very slow. May I know MARSS simulation speed?
Thanks
On Tue, Oct 23, 2012 at 2:26 AM, Andreas Hansson wrote:
> Hi Benjamin,
>
> The list is long…gem5 has (amongst other things):
>
> a variety of CPU models that
Hi all,
Since a long time ago, I have this message when I run my simulation with
restoring from the checkpoints I have taken (also a long time ago):
warn: Checkpoint ver 0 is older than current ver 0x1
warn: You might experience some issues when restoring and should run the
checkpoi
GE ZHIGUO writes:
> Hi,
> Can you figure out the source code which causes this problem.
As I said, it's routines _spin_lock_irq and _spin_lock_irqsave.
Here's the generated code (most of it appears to come from __ticket_spin_lock):
805f0c40 <_spin_lock_irqsave>:
805f0c40:
Should I save the results only for the mispredicted ones or for all
branches ?
If I only have to save the results for the mispredicted ones then the
condition is that gem5 to be deterministic (so the miss happens at the same
simulation cycle between multiple SE cycles). Is gem5 SE deterministic ?
Thanks Andreas.
On Tue, Oct 23, 2012 at 4:36 PM, Andreas Hansson wrote:
> Mitch is spot on I think.
>
> The latencies are for that specific block, caches, busses, memory
> controllers etc.
>
> Andreas
>
> From: mihai pricopi mihai.pric...@gmail.com>>
> Reply-To: gem5 users mailing list gem5-use
Mitch is spot on I think.
The latencies are for that specific block, caches, busses, memory controllers
etc.
Andreas
From: mihai pricopi mailto:mihai.pric...@gmail.com>>
Reply-To: gem5 users mailing list
mailto:gem5-users@gem5.org>>
Date: Tuesday, 23 October 2012 09:35
To: gem5 users mailing l
Thanks :) indeed I think is the only way possible.
Can I ask one more question regarding L2 and memory latency ?
For a L2 cache access the latency is computed by (L1.latency + L2.latency)
or is the L2.latency ?
Similarly for memory ?
On Tue, Oct 23, 2012 at 10:54 AM, Mitch Hayenga <
mitch.hayeng
How about *not to* push cache latencies in to the queue? Though I am not
quite sure about if this is correct.
Regards,
Mahmood
On Mon, Oct 22, 2012 at 10:58 PM, Runjie Zhang wrote:
> Greetings,
>
> I tried to write stressmarks in X86 assembly so that the simulated IPC
> or O3CPU can hit N f
Hello,
What you're looking for is here: http://www.m5sim.org/M5ops
You need to include a header file on your code and call functions to
dump stats and/or reset them. You'll also need to include a .S file in
your makefile.
Hope it will help.
2012/10/23, shervin hajiamini :
>
>
> Hi all,
>
>
> For
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