Mitch is spot on I think.

The latencies are for that specific block, caches, busses, memory controllers 
etc.

Andreas

From: mihai pricopi <mihai.pric...@gmail.com<mailto:mihai.pric...@gmail.com>>
Reply-To: gem5 users mailing list 
<gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
Date: Tuesday, 23 October 2012 09:35
To: gem5 users mailing list <gem5-users@gem5.org<mailto:gem5-users@gem5.org>>
Subject: Re: [gem5-users] Perfect branch predictor in ooo

Thanks :) indeed I think is the only way possible.

Can I ask one more question regarding L2 and memory latency ?

For a L2 cache access the latency is computed by (L1.latency + L2.latency) or 
is the L2.latency ?
Similarly for memory ?

On Tue, Oct 23, 2012 at 10:54 AM, Mitch Hayenga 
<mitch.hayenga+g...@gmail.com<mailto:mitch.hayenga+g...@gmail.com>> wrote:
No, that would not be enough.  Doing that change would just make the front end 
assume no branch was ever taken (and the sim would actually crash because the 
commit logic would later would try to inform the front end about branches it 
never predicted).

To do this (with the saving branch outcomes to a file & later just replaying 
them as if you had predicted them right the first time), you'd have to hook the 
proper spaces in the squash/update functions in bpred_unit_impl.hh to figure 
out what the correct predictions should have been.  Then save these correct 
decisions off to a gzipped file (I haven't thought how big this is going to be, 
but this file will be pretty massive).  Then re-run the simulation with the 
"predict" from bpred_unit_impl.hh just feeding the correct path information 
from this file.


On Mon, Oct 22, 2012 at 9:14 PM, mihai pricopi 
<mihai.pric...@gmail.com<mailto:mihai.pric...@gmail.com>> wrote:
Thanks.
Would be enough to change a bit the lookupAndUpdateNextPC() function such that 
the return is always false ?
I mean changing the:

    if (!inst->isControl()) {
        TheISA::advancePC(nextPC, inst->staticInst);
        inst->setPredTarg(nextPC);
        inst->setPredTaken(false);
        return false;
    }


to

//    if (!inst->isControl()) {
        TheISA::advancePC(nextPC, inst->staticInst);
        inst->setPredTarg(nextPC);
        inst->setPredTaken(false);
        return false;
 //   }

 ?


On Tue, Oct 23, 2012 at 10:02 AM, Mitch Hayenga 
<mitch.hayenga+g...@gmail.com<mailto:mitch.hayenga+g...@gmail.com>> wrote:
Since gem5 the O3 cpu model actually executes instructions @ execute (not 
fetch/decode) a perfect branch predictor is a bit tricky.  Assuming you are 
running a single-threaded app in SE mode (so you don't have OS/multi-threaded 
time variance issues), you could simply run the application twice.  Save the 
branch outcomes from the first run.  Then re-run the app, with a "predictor" 
that just uses the branch results from the first time you ran the application.

On Mon, Oct 22, 2012 at 8:43 PM, mihai pricopi 
<mihai.pric...@gmail.com<mailto:mihai.pric...@gmail.com>> wrote:
Hi,

 I am using arm_detailed SE mode.
 Is there a simple way to force the branch predictor to do perfect prediction ?

Thanks

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