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Andrew Poelstra wrote:
> On Sat, Aug 06, 2011 at 11:16:11PM +0200, Kai-Martin Knaak wrote:
>>
>> The procedures with no_drc look unchanged. I still don't see a way
>> to make this work. I give up and write a bug report.
>>
>
> Bump.
Rebump.
> (
On Sat, 13 Aug 2011 19:34:38 +0200
Levente Kovacs wrote:
> On Fri, 5 Aug 2011 17:36:25 + (UTC)
> Sparky wrote:
>
> > For my outline layer I did the following to add the attribute:
> > Edit->Edit attribute of->CurrentLayer
> > Left box: PCB::skip-drc
> > Right box: 1
>
> I'm sorry fo
On Fri, 5 Aug 2011 17:36:25 + (UTC)
Sparky wrote:
> For my outline layer I did the following to add the attribute:
> Edit->Edit attribute of->CurrentLayer
> Left box: PCB::skip-drc
> Right box: 1
I'm sorry for the late answer.
I'm not sure if you need this for the layer called "outli
Andrew Poelstra wrote:
>> The procedures with no_drc look unchanged. I still don't see a way
>> to make this work. I give up and write a bug report.
>>
>
> :(
Of course, I still have to satisfy the design rules of my fab. My board
is 100 µm copper on inner layers and 35 mm on outer. The fab r
On Sat, Aug 06, 2011 at 11:16:11PM +0200, Kai-Martin Knaak wrote:
>
> The procedures with no_drc look unchanged. I still don't see a way
> to make this work. I give up and write a bug report.
>
Bump.
(Whenever I get a chance, if you have not reported this, then I
will. But that might not be f
On Sat, Aug 06, 2011 at 11:16:11PM +0200, Kai-Martin Knaak wrote:
> Andrew Poelstra wrote:
>
> > Kai, just for fun, you might want to try with the nanometers
> > branch:
> >
> > git clone git://wpsoftware.net/pcb-andrew.git
>
> I did and it compiled right away.
>
>
> > checkout branch coord5
Kai, just for fun, you might want to try with the nanometers
branch:
git clone git://wpsoftware.net/pcb-andrew.git
checkout branch coord5. If you don't want the actual conversion,
checkout coord5^. It has a fairly cleaned-up find.c that should
behave the same way, but be a little easier to trace
On Sat, Aug 06, 2011 at 05:23:59PM +0200, Kai-Martin Knaak wrote:
>
> The continue statement completely messes the DRC check. I get more
> violations with PCB::skip-drc than without. Seems like the if-statements
> have some side effect that should not be skipped. What does the r_search
> line act
Andrew Poelstra wrote:
> Hmm, at a glance this looks okay.
> Can you change the loop to
> dump some debug code before each continue, like, say,
>
> if (LAYER_PTR (layer)->no_drc)
> {
> fprintf (stderr, "Skip layer %d, max %d, (PVL.L %d, PVL.N %d)
> continuing...\n",
> layer
On Fri, Aug 05, 2011 at 02:05:14PM -0400, DJ Delorie wrote:
>
> Yup, namespaces. Each app/module/whatever should have its own
> namespace, although I'm not picky about the syntax as long as it's
> consistent.
>
> "PCB::grid-units" ""
> "grid::units"
>
> etc.
>
> It makes sense for all of PCB's
Yup, namespaces. Each app/module/whatever should have its own
namespace, although I'm not picky about the syntax as long as it's
consistent.
"PCB::grid-units" ""
"grid::units"
etc.
It makes sense for all of PCB's built-in ones to use PCB:: leaving
other namespaces for plugins and external apps
On Fri, Aug 05, 2011 at 07:28:34PM +0200, Kai-Martin Knaak wrote:
> Kai-Martin Knaak wrote:
>
> > Unfortunately, current git head of PCB enters an infinite loop if
> > the attribute is set correctly. The attached patch fixes this bug.
> > Now, DRC does indeed ignore the layers marked by the attrib
Levente Kovacs writes:
>
> If you add the attribute
>
> PCB::skip-drc
>
> to a layer, that won't be checked against DRC, and commections.
>
> Levente
>
> On Wed, 3 Aug 2011 23:56:23 -0700
> Colin D Bennett wrote:
>
> > On Thu, 04 Aug 2011 01:48:09 +0200
> > Kai-Martin Knaak wrote:
> >
>
Kai-Martin Knaak wrote:
> Unfortunately, current git head of PCB enters an infinite loop if
> the attribute is set correctly. The attached patch fixes this bug.
> Now, DRC does indeed ignore the layers marked by the attribute.
> ( I triple checked ;-)
Well, it was working for a smallish pet proj
On Fri, 05 Aug 2011 04:32:58 +0200
Kai-Martin Knaak wrote:
> Kai-Martin Knaak wrote:
> The correct syntax is:
> Attribute("PCB::skip-drc" "1")
>...
> By the way, what is the reason for the funny attribute name
> with two colons in the middle? The source treats it just like
> a plain strin
Kai-Martin Knaak wrote:
> Just tried it and it works great :-)
I was a victim of wishfull thinking. Seems like I did not set the
attribute successfully. As a result, the no_drc code path was not
entered at all. I must have fooled myself with settings.
> For the archive: Syntax in the *.pcb fi
On Thu, 4 Aug 2011 15:09:22 +0200
Levente Kovacs wrote:
> If you add the attribute
>
> PCB::skip-drc
>
> to a layer, that won't be checked against DRC, and commections.
That's great! But, the Optimize Rats ('o' key) detection of shorted
nets would need to somehow use this, if it is to solve t
Levente Kovacs wrote:
> If you add the attribute
So it is already implemented!
Just tried it and it works great :-)
There is just nothing in the GUI or in the manual that hints to it. Talk
about discoverbility.
With the proper keywords I found the mail to this list where you announced
a reb
If you add the attribute
PCB::skip-drc
to a layer, that won't be checked against DRC, and commections.
Levente
On Wed, 3 Aug 2011 23:56:23 -0700
Colin D Bennett wrote:
> On Thu, 04 Aug 2011 01:48:09 +0200
> Kai-Martin Knaak wrote:
>
> > Colin D Bennett wrote:
> >
> > > A feature I have hea
On Thu, 04 Aug 2011 01:48:09 +0200
Kai-Martin Knaak wrote:
> Colin D Bennett wrote:
>
> > A feature I have heard previously requested is to be able to mark
> > certain layers as “no-DRC”. For instance, to allow special trace
> > elements such as antennas that the DRC thinks are incorrect shorts
Colin D Bennett wrote:
> A feature I have heard previously requested is to be able to mark
> certain layers as “no-DRC”. For instance, to allow special trace
> elements such as antennas that the DRC thinks are incorrect shorts
> between two nets.
These should be omited from update_rats, rather t
On Wed, 03 Aug 2011 16:24:21 +0200
Kai-Martin Knaak wrote:
> Hi.
> My current project calls for big currents and and fine pitch SMD
> components, too. So I opted for four layers with 35 µm copper on
> outer and 105 µm copper on inner layers. Now, my fab requests 250 µm
> clearace on layers with
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