On Wed, 03 Aug 2011 16:24:21 +0200 Kai-Martin Knaak <kn...@iqo.uni-hannover.de> wrote:
> Hi. > My current project calls for big currents and and fine pitch SMD > components, too. So I opted for four layers with 35 µm copper on > outer and 105 µm copper on inner layers. Now, my fab requests 250 µm > clearace on layers with extra copper. To comply with this, it would > be handy to have different sets of design rules fpor differnt layers. > > In the absence of that feature, is there any way to restrict a DRC > check just to one specific layer? A feature I have heard previously requested is to be able to mark certain layers as “no-DRC”. For instance, to allow special trace elements such as antennas that the DRC thinks are incorrect shorts between two nets. I also would like this so that the “outline” layer or extra layers with my own notes, calculations, fab notes, etc., are not considered for DRC. Regards, Colin _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
