Friends -
On Wed, Aug 17, 2011 at 12:43:50AM +0200, Kai-Martin Knaak wrote:
> Colin D Bennett wrote:
> > For instance, here
> > are some footprint file names from my library:
> >
> > Abracon_ABM8G.fp
> > ADAM_TECH_2PH_2.00_mm_pin_header_SMT_2_pin.fp
> > ADAM_TECH_2PH_2.00_mm_pin_header_SMT_3_pin.
On Thu, Aug 04, 2011 at 02:25:05PM -0400, DJ Delorie wrote:
> > What desktop are you using for gEDA?
> I'm using fvwm2 but my setup is far from normal in many ways ;-)
evilwm FTW! Unless someone out there is using ratpoison. :-p
Ditto about my setup. ;-)
- Larry
__
John -
On Tue, Jul 26, 2011 at 01:07:51PM -0500, John Griessen wrote:
> Larry Doolittle is going to be there in person. What can we tell them
> to get them interested in gEDA more than KiCAD?
Not push and shove, unless someone (not me) goes wild
programming between now and October.
I h
Friends -
On Thu, May 26, 2011 at 01:41:08PM -0700, Jared Casper wrote:
> On Thu, May 26, 2011 at 11:52 AM, Andrew Poelstra wrote:
> > On Thu, May 26, 2011 at 10:56:40AM -0400, DJ Delorie wrote:
> >> I'm a Perl fan myself.
> > I think Python would be a better choice.
> Scala anyone?
It's probabl
On Sat, May 21, 2011 at 09:19:21AM -0400, Bob Paddock wrote:
> On Sat, May 21, 2011 at 9:09 AM, Kai-Martin Knaak wrote:
> > My proposal to tackle many of the library related issues is the notion
> > of packages. These would be data structures that can contain all information
> > relevant to an ent
Peter -
On Wed, Apr 20, 2011 at 12:55:31PM +0100, Peter Clifton wrote:
> On Tue, 2011-04-19 at 21:34 -0700, Larry Doolittle wrote:
> > My RF gear makes a plausible "vector oscilloscope"
> Sounds awesome, can you post some pictures - screen-shots and HW?
I've plugged
Rick -
On Tue, Apr 19, 2011 at 10:27:54PM -0400, rickman wrote:
> ... Providing a real time display with a high
> update rate would be a challenge for me. If that part is done, then
> the first major hurtle is done. Some part of the hardware design
> depends on what the software requires to faci
On Mon, Apr 11, 2011 at 10:43:08PM +0100, Peter Clifton wrote:
> On Mon, 2011-04-11 at 12:37 -0700, Larry Doolittle wrote:
> > Surely you can convert SVG to EPS, which TeX/LaTeX happily embed.
> > http://sk1project.org/modules.php?name=Products&product=uniconvertor
> I use pd
On Mon, Apr 11, 2011 at 08:55:12PM +0200, Kai-Martin Knaak wrote:
> Peter Clifton wrote:
>
> > TBH, I've not seen SVG anywhere on the main-stream internet.
>
> Wikipedia prefers SVG for anything that is not a photograph. The servers
> render SVG graphics to PNG as needed before handing it out to
Friends -
On Thu, Apr 07, 2011 at 01:52:10PM +0200, Kai-Martin Knaak wrote:
> DJ Delorie wrote:
> >> python. It only does SMD dual column footprints with an outline -
> >> and at the moment only takes mm.
> > Seems to be a popular thing to do. I did one a while ago, and mine
> > wasnt the first
Hi -
The nice pages that Anthony Blake had up describing
his toporouter efforts are currently unavailable.
Anthony, can you kick your server?
If anyone has an out-of-band method of reaching Anthony,
can you point this out? And if someone has a mirror up
somewhere, can you post a link?
http://w
On Sat, Mar 26, 2011 at 08:50:36PM -0400, Patrick Doyle wrote:
> I'm looking for a US distributor for a Balloon Board
Kind of orthogonal question, how about the MilkyMist One?
http://www.milkymist.org/mmone.html
It doesn't have a separate processor chip, they
implement their own processor in the
On Fri, Feb 25, 2011 at 12:32:13PM -0500, DJ Delorie wrote:
> > So, could you, pretty please, point me to some nice C++ code.
> Sorry, the work I did back then was not OSS. I'll have to write some
> more "nice C++" for you :-)
Tastes may vary, but some years ago when I went looking for a clean
C+
On Thu, Feb 24, 2011 at 01:29:08PM -0800, Colin D Bennett wrote:
> On Thu, 24 Feb 2011 20:48:39 +
> Peter Clifton wrote:
> > You could add it to PCB I guess - we could even teach PCB how to
> > invoke the compiler and build plugins if we were feeling over-keen!
> > (But perhaps that is encroac
On Thu, Feb 24, 2011 at 09:23:44AM -0700, Russell Dill wrote:
> On Thu, Feb 24, 2011 at 8:50 AM, Peter Clifton wrote:
> > On Thu, 2011-02-24 at 08:38 -0700, John Doty wrote:
> >> On Feb 24, 2011, at 8:22 AM, Peter Clifton wrote:
> >> > Means C didn't find the function, and it assumes it returns in
Friends -
On Wed, Nov 17, 2010 at 11:12:46PM -0800, Larry Doolittle wrote:
> I have a new release of vhd2vl pretty much ready to post.
Version 2.4 is now posted at the usual place:
http://doolittle.icarus.com/~larry/vhd2vl/
Enjoy!
- La
distribute!!!) (Larry Doolittle,
November 2010)
Grammar:
* Drop DOS-style returns at end of comments
* Allow FLOAT in expressions (maybe a mistake)
* fixed regression in "others" handling since 2.1
(the following were submitted by Shankar Giri)
* Verilog 2001 module declarati
DJ -
On Mon, Nov 08, 2010 at 05:55:04PM -0500, DJ Delorie wrote:
> > A JTAG bit-banger is not hard to write (I've written at least two of
> > them), and a lot smaller than an xsvf file player.
> Can you bit-bang a spartan 3 that way?
Yes. Shameless plug (and almost back OT, since the board was
l
On Mon, Nov 08, 2010 at 05:24:21PM -0500, DJ Delorie wrote:
> True, but the xsvf file is much bigger than a simple serial bitstream,
> and the xsvf player is bigger than a raw spi dump...
A JTAG bit-banger is not hard to write (I've written at least two of
them), and a lot smaller than an xsvf fil
On Mon, Nov 08, 2010 at 05:09:30PM -0500, DJ Delorie wrote:
> > Just boot the FPGA from the processor. That's what I always do.
> > When I have a processor, that is. The only overhead is the four
> > GPIO pins attached to the FPGA JTAG, and those can be put to good
> > use after booting as well.
DJ -
On Mon, Nov 08, 2010 at 04:46:35PM -0500, DJ Delorie wrote:
> > That's unfortunate. I've been getting some good mileage out of the
> > XC3S200A-VQ100 parts. Too bad Xilinx hasn't made that size available in
> > the 3AN family. I suppose that you chose the AN variant because you
> > wanted
Rick -
On Mon, Sep 06, 2010 at 10:31:15PM -0400, Rick Collins wrote:
>> Several times now in this thread I keep thinking that the language Forth is
>> being described. 'Words' built up on previously defined 'words'...
> I have often thought that I would prefer to write an HDL that works like
> F
On Mon, Aug 16, 2010 at 07:32:23PM +0200, Stephan Boettcher wrote:
> I usually have hierarchical schematics with multiple instances of the
> same subcircuits referenced from the main page. The deepest until now
> were three layers of hierarchy.
I make do with two, but that's how I work also.
> A
On Wed, Aug 04, 2010 at 10:58:51AM -0400, Patrick Doyle wrote:
> Can anybody tell me if the following is an Icarus feature or a Verilog
> feature.
Verilog. Probably.
> reg [5:0] offset;
> reg [9:0] enablemask;
>initial begin
> enablemask = 10'b0_00110;
> offset = 0;
>
On Tue, Aug 03, 2010 at 09:12:00AM -0400, Patrick Doyle wrote:
> I have some verilog test code in which I would like to display an
> integer value, which is known to be between 0 and 15, as a binary
> vector, i.e.
>
> integer result;
> $display("%4b", result);
>
> of course I get a 64 bit vector
On Thu, Jul 22, 2010 at 09:57:11AM -0700, Steven Michalske wrote:
> On Jul 22, 2010, at 9:50 AM, Eric Brombaugh wrote:
> > On 07/22/2010 09:37 AM, DJ Delorie wrote:
> >>
> >> One idea to consider is to start with a solid plane, and cut slots
> >> around the sensitive analog parts, like big C shap
On Mon, May 03, 2010 at 03:14:22PM +, Kai-Martin Knaak wrote:
> You don't need a data base for this kind of indirection. Any download
> script would do. However, it makes the process depend on stability of
> external sources --sources that can change, or go away without any day.
> Experience
Dave -
On Fri, Apr 23, 2010 at 12:15:36PM -0400, Dave McGuire wrote:
>> Lots of people speak Esperanto.
> It's all relative. Compared to, say, Spanish?
>> I'm one of them. Multaj homoj parolas Esperanton. Mi estas unu el ili.
> Very cool. Translation?
Come on, Dave. Pattern match.
Multaj
On Sun, Apr 18, 2010 at 08:38:28PM -0700, Larry Doolittle wrote:
> Sent privately, maybe you can summarize responses
Yeah, well, I got distracted at exactly the wrong moment.
So kick me.
- Larry
___
geda-user mailing list
geda-user@moria.seul.
Jared -
Sent privately, maybe you can summarize responses
(or if I'm the only one, tell me, and I'll post
to the list).
On Sun, Apr 18, 2010 at 04:05:16PM -0700, Jared Casper wrote:
> I think it makes the build much cleaner and readable overall and, more
> importantly, makes the errors and warnin
Rob -
On Mon, Mar 29, 2010 at 11:14:51AM -0400, Rob Butts wrote:
>I've read about the eddy current breaks but it's still not clear to me
>how to construct one. The wikipedia talks about a rotor connected to a
>spinnning coil. I would think the rotor would spin inside a coil.
Any tim
Al -
On Wed, Mar 03, 2010 at 10:18:59AM -0500, al davis wrote:
> Along that line ... You could get what they call "reading
> glasses" from a supermarket. Get the strongest ones they have.
> They make great magnifying glasses.
I didn't need them in college, but I sure need them now!
> You re
On Sat, Feb 27, 2010 at 09:03:41AM -0500, Bob Paddock wrote:
> The other thing that is holding back gEDA Schematics is the lack of
> available publication quality symbols. If I'm doing a PCB I use gEDA.
> If I'm after a nice looking schematic I use XCircuit. I'd like to be
> able to have it both
Hi -
On Wed, Feb 24, 2010 at 02:40:50PM -0500, Bob Paddock wrote:
> I'm making the assumption you will have a contractor build quantities someday,
> in automated equipment. These will (at least should) lower production costs:
Although OT, I appreciate and try to learn from discussions like this.
Like others in this group, I'm a TeX partisan, and yes that
includes pdftex most of the time. I converted to TeX from
VAX runoff in 1987.
On Sat, Feb 06, 2010 at 12:10:04PM +, Peter Clifton wrote:
> pdflatex also supports .png and .jpg files natively - which is
> (probably) better than .eps f
Tony -
On Mon, Jan 25, 2010 at 10:18:07AM -0500, Tony Radice wrote:
> I have written a Perl script to extract pick and place data from a
> pcb file - is anyone else interested in looking at it, using it or
> critiquing it?
You know pcb already has a pick and place data extractor?
This is the
On Mon, Nov 16, 2009 at 01:19:44PM +0900, Torsten Wagner wrote:
> a) just buy a bigger machine and use virtualisation technologies [chop]
> b) get some of this little ARM based boards or Atom based boards [chop]
> c) Computers which does not need to run 24/7 but always on because [chop]
d) Replace
Neil -
On Mon, Oct 19, 2009 at 01:20:23PM -0700, Neil Hendin wrote:
> If you look at the RF S-Parameters of the capacitor at frequencies
> above the self resonance, they look inductive, not capacitive.
I'm not sure what the precise definition is for the S-Parameters
of a two-terminal device, but
John -
On Fri, Sep 25, 2009 at 10:27:02AM -0600, John Doty wrote:
> Remember, "pcb" is a separate tool, not part
> of gEDA.
But it does fall under the gaf umbrella, and this is the
proper mailing lists for things pcb-related.
> Probably very few pcb users capture schematics with anything
> b
On Sun, Sep 20, 2009 at 06:00:11PM +, Michael Sokolov wrote:
> In my code of honor a PCB designer who lays out an Open Source Hardware
> board deserves to have his/her name on the silk screen, at least on the
> bottom side if there is no room on the top component side.
I personally think autho
DJ -
On Sun, Aug 09, 2009 at 01:22:20PM -0400, DJ Delorie wrote:
> > It's in the Edit menu, called "Expand" (F3).
> Sweet. Hmmm... "Expand" again on one of those individual lines should
> re-combine them.
No, you have to select a bunch of individual signals
(they need not be the full set of the
DJ -
On Sun, Aug 09, 2009 at 05:51:40AM -0400, DJ Delorie wrote:
> The LA module I wrote is a DDR dual-bank capture, [chop]
> A perl script turns them into a VCD file that gtkwave can read :-)
Awesome. I hope you'll write this up more, and publish code.
> Question: Can gtkwave be told to break
Bill -
On Sun, Jun 28, 2009 at 12:26:10PM -0500, Bill Gatliff wrote:
> [greatly trimmed]
> It would be nice if there was an
> additional "layer of abstraction" somewhere between the symbol and
> footprint, such that actual pin assignments weren't made until the
> footprint (and slot, if necessary)
Michael -
On Fri, Jun 19, 2009 at 06:52:14AM +, Michael Sokolov wrote:
> Ineiev wrote:
> > BTW why unplated holes may be preferable for this case?
> [pcbfabexpress.com] charge $50 extra for unplated drill and I'm OK with
> that. (That's for the whole order, not per board.)
That's payment so
Michael -
On Fri, Jun 19, 2009 at 02:52:10AM +, Michael Sokolov wrote:
> * Both plated and unplated drill. Some parts have plastic mounting
> elements and I want unplated holes for those.
Get all your holes plated and drill out your mounting holes
by hand. Otherwise you will end up with a
Saritha -
On Wed, May 20, 2009 at 01:47:03PM -0700, Saritha Kalyanam wrote:
>3) escape routing for BGA?
Here's a start:
http://recycle.lbl.gov/~ldoolitt/ft256/
(or finish, for that particular device)
Generalized, it represents normal industry practice.
- Larry
__
Patrick -
On Thu, Apr 09, 2009 at 10:01:06AM -0400, Patrick Doyle wrote:
> For those of you who might be interested... I found the bug in my
> verilog code that was triggering the crash. I had a spelling mistake
> in one of my nets that resulted in a net being implicitly declared.
> Personally, I
Patrick-
On Thu, Apr 09, 2009 at 08:23:55AM -0400, Patrick Doyle wrote:
> I tried firing up gdb on iverilog, but that doesn't do much good, as
> iverilog is simply the driver program. Is there a howto one can point
> me at for debugging iverilog?
see email from Steve Tue, 05 Jun 2007 12:33:19 -0
On Mon, Apr 06, 2009 at 09:42:30AM -0700, Eric Brombaugh wrote:
> I've had no trouble installing the full ISE on Fedora and I've been
> using it since 2005 or so. Webpack's installer is limited to 32-bit
> systems though, so if you're on a 64-bit system that might be getting in
> your way.
It's
DJ -
On Fri, Mar 27, 2009 at 04:29:12PM -0400, DJ Delorie wrote:
> [the XC9536XL is] huge compared to a 16v8, though,
> but once you have the bitstream
> files (xilinx runs with Makefiles on Linux) you can program them with
> open source or home-brew toools.
Funny, I was just trying to hack my Xi
On Mon, Mar 09, 2009 at 12:40:47PM -0500, John Griessen wrote:
> Its hard to pick a set of single letter names to use as instance names to use
> with a ""
> separator, since so many are "used up" by first letters of component names:
> Cap Diode Fuse J(connector) L(inductor)
> Q(transistor) Resist
On Sun, Mar 08, 2009 at 06:41:31PM -0400, DJ Delorie wrote:
> > is there any type of regression test suite for PCB?
> Nope.
That, itself, sounds like a bug.
- Larry
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mail
Patrick -
On Tue, Mar 03, 2009 at 12:37:17PM -0500, Patrick Doyle wrote:
> developers eventually added their own Verilog extension, the
> VPI function $finish_and_return(exit_status).
>
>Oh... I like that!
>That's just what I was hoping my buddy Google would have found for
>
Patrick -
On Tue, Mar 03, 2009 at 11:39:28AM -0500, Patrick Doyle wrote:
>I have an Icarus Verilog question (which may, perhaps be a more
>general Verilog question). I would like to write a test bench that
>exits with a non-zero status when it detects an error. That way I can
>si
Friends -
Check out
http://doolittle.icarus.com/~larry/vhd2vl/
for a new release (v2.2) of vhd2vl.
User-visible features relative to Mark Gonzales' version 2.0:
* add XNOR
* add hex strings (X"f0f0")
* remove UNIT reserved words, and actually emit timescale directive
* case statements w
Eric -
On Fri, Feb 27, 2009 at 11:32:40AM -0700, Eric Brombaugh wrote:
> As far as kits go, sorry. I'm not set up to sell parts (there are
> probably about $70 worth on this board if bought in small qty). If you'd
> like to take the gerbers to your own fab though feel free to do so. It
> cost m
Dan -
On Tue, Feb 17, 2009 at 10:01:57PM -0500, Dan McMahill wrote:
> The tool worked and really my primary complaint was that you quickly
> ended up with an expression that
> a) was not at all a low entropy expression (see various papers by
> Middlebrook or the textbook by Vorperian)
Hey! I s
Gabriel -
On Tue, Feb 17, 2009 at 03:47:10PM +0100, Gabriel Paubert wrote:
> Did not nee for this, and my RF designs use Rogers' substrates which
> are much more reproducible than FR4 at frequencies above 2GHz.
I'm currently searching for a U.S. fab for prototype quantity
of Rogers' boards that d
Peter -
On Wed, Feb 11, 2009 at 03:39:23PM +, Peter Clifton wrote:
> On Wed, 2009-02-11 at 09:44 -0500, Joshua Boyd wrote:
> > Either with or without my change to Makefile.am, aclocal complains with
> > a lot of warnings:
>
> I've noticed more and more noise from aclocal on Ubuntu systems. It
Levente -
On Wed, Feb 04, 2009 at 11:30:53PM +0100, Levente Kovacs wrote:
> I would like to print labels. For this I'd generate N times some labels, with
> slight different content. Then I have N *.eps file.
>
> Question. How do I merge them into one A4 postscript page?
Look into mpage
http:/
On Mon, Jan 26, 2009 at 02:32:18AM +, Peter Clifton wrote:
> On Sun, 2009-01-25 at 17:21 -0800, Gary L. Roach wrote:
> > [chop] I'm running 1;1.4.0-2 on Lenny.
> I presume by reinstalled, you mean that you re-installed the debian
> package, not installed from source. [chop]
Speaking of Debian/
Friends -
On Sat, Jan 24, 2009 at 12:52:27AM +, Peter TB Brett wrote:
> On Saturday 24 January 2009 00:43:10 John Griessen wrote:
> > Giuseppe Dia wrote:
> > > just a quick message to say I've founded a gEDA group on Linkedn called
> > > gEDA professionals .
> > See http://www.linkedin.com/gr
John -
On Tue, Jan 13, 2009 at 12:54:21PM -0700, John Doty wrote:
> It seems you want gEDA to cater to your unwillingness to master new
> skills, learn better ways to do things. But gEDA's power is that it
> frees you to use the better way, not constraining you to inefficient
> ways of doing
On Fri, Jan 02, 2009 at 09:40:08PM -0700, Eric Brombaugh wrote:
> I've been glancing over some of the inexpensive Linux-based
> netbooks lately - a tad underpowered, but potentially useful and cheap
> enough to take a flyer on. I'm curious how useful a 1024x800 screen
> would be for gEDA/PCB.
On Fri, Dec 26, 2008 at 02:01:12PM -0800, Dave N6NZ wrote:
>
> One thing I've always liked about the Thinkpad's/Lenovo's is the
> excellent feel and behavior of the "pressure stick". Works great. My
> new Lenovo has both a stick (which I like and use) and also a scratcher,
> which keeps getti
Stuart -
On Fri, Dec 26, 2008 at 07:33:13AM -0500, Stuart Brorson wrote:
> Ordinarily I'd buy a reconditioned IBM Stink Pad from IBM, and then
> stick Fedora on it. Stink Pads are mechanically robust, and they play
> with Linux easily. However, IBM has sold the Stink Pad division to
> China, and
DJ -
On Wed, Nov 12, 2008 at 12:03:13AM -0500, DJ Delorie wrote:
> I'm not sure how much smarts I can put in an R8C/20. The biggest
> available one has 64k of flash and 3k of RAM. I was thinking of using
> just UDP - that gives me DHCP, sNTP, and a way to send back
> measurements.
>
> OTOH if a
John -
On Tue, Oct 28, 2008 at 10:11:38PM -0500, John Griessen wrote:
> Larry Doolittle wrote:
> > I have seen exactly one case where a "split" (very carefully done)
> > on the ground plane was needed to avoid a source of ground return
> > crosstalk.
> I'
On Tue, Oct 28, 2008 at 07:07:18PM -0400, John Luciani wrote:
> On Tue, Oct 28, 2008 at 6:53 PM, DJ Delorie <[EMAIL PROTECTED]> wrote:
> >> Don't you have a number of PCs running 24x7?
> > Yup, at least six of them.
> If you need another fun project ---
>
> Rack mount power distribution box with a
Joerg -
On Tue, Oct 28, 2008 at 02:07:30PM -0700, Joerg wrote:
> Tried to load your layout but got an error and I could not find any
> pointers via web search.
>
> Error parsing file ...
> line: 801
> description: font position out of range
I hit this too. I just deleted the Symbol that tarts
DJ -
On Tue, Oct 28, 2008 at 12:49:51PM -0700, Larry Doolittle wrote:
> Your board looks decent. What kind of voltage resolution are you
> looking for (e.g., what IC are Uxx0)?
I see now, ADE7753ARSZ, $3.834 in 25's at DigiKey. 16-bit Sigma-Delta
under the hood. Good luck with t
DJ -
On Tue, Oct 28, 2008 at 03:09:37PM -0400, DJ Delorie wrote:
> > App notes and example designs are special cases: there is only
> > one chip straddling the analog and digital divide. If you have
> > more than one (e.g., both an ADC and a DAC) all those ideas
> > pretty much go out the window,
On Tue, Oct 28, 2008 at 02:49:37PM -0400, DJ Delorie wrote:
>
> > In my 20+ years in engineering I have yet to see one case where
> > splitting a ground plane under high-speed ADCs has worked.
>
> What about high precision ADCs? I'm working on a design using ADE7753
> power monitor chips (16-bit
Marvin -
On Tue, Oct 21, 2008 at 12:16:01AM -0400, Marvin Dickens wrote:
> I made an SFP footprint couple of years ago for a project. As I recall,
> this is a 20 pin DIP package with .8mm pitch
Right, but the two rows are staggered. And then there is the cage
to deal with.
> Let me look back th
Friends -
Just wondering how lazy I can be:
Has anyone here made an SFP footprint for PCB?
(SFP = Small Form-factor Pluggable transceiver,
http://en.wikipedia.org/wiki/SFP_transceiver)
(e.g., AMP UE75-A20-3000T plus U77-A4114-2001)
Has anyone here connected such a device to
a Xili
Guys -
On Sun, Sep 21, 2008 at 08:53:29PM -0400, evan foss wrote:
> On 9/21/08, Stuart Brorson <[EMAIL PROTECTED]> wrote:
> > But I did see this strange contraption from the street:
> > http://www.luciani.org/photos/pic1/2008-09-21-mit-flea/IMG_1612.JPG
> > Do you have any idea what it is?
> I
Evan -
On Sun, Sep 07, 2008 at 02:51:48AM -0400, evan foss wrote:
> I just have to wonder aloud what would happen if someone made a beer
> that was actually open sourced. Stallman would have to make a new
> saying to avoid confusion.
http://www.freebeer.org/
http://en.wikipedia.org/wiki/Open_Sourc
Jean -
On Sat, Sep 06, 2008 at 01:17:14PM -0400, jean wrote:
> Is there anyway in pcb to measure the length of the traces and
> see how different they are? I'd like to have them match up as close as
> possible instead of just eyeballing it.
Yes. Report(NetLength), added 2007-03-03 by djdelorie.
Guys -
On Sat, Aug 30, 2008 at 07:38:06AM -0400, Bob Paddock wrote:
> On Friday 29 August 2008 11:15:03 pm Robert Butts wrote:
> > I'm using ten [laser diodes in] parallel. I WAS going to
> > just use a 1 amp 5 vdc power supply with a 2.8 V zener diode
> > to adjust the voltage to 2.2 V.
>
> Doe
On Sun, Jul 20, 2008, [redacted] wrote:
> On Sat, Jul 19, 2008 at 1:09 AM, Larry Doolittle <[EMAIL PROTECTED]> wrote:
> > OK, really stupid question: is there a "standard" suffix
> > to use for Verilog include files? [chop]
> Where I work (a large and very w
Friends -
OK, really stupid question: is there a "standard" suffix
to use for Verilog include files? I need something different
from .v, so my Makefiles and scripts can tell them apart:
include files don't get listed on the Icarus command line,
even though they are a dependency listed in the Make
On Mon, Jun 30, 2008 at 12:00:48AM -0400, al davis wrote:
> On Sunday 29 June 2008, John Doty wrote:
> >
> > > It looks to me that geda has mixed the concepts of
> > > discipline and direction.
> >
> > Yes, but the real problem is the mixing of such clerical
> > concepts into what is really a set o
l device support for MAX1202, MAX5742, TCN75, and ADF4001
// $Id$
// Larry Doolittle, LBNL
// llc-suite Copyright (c) 2004, The Regents of the University of
// California, through Lawrence Berkeley National Laboratory (subject
// to receipt of any required approvals from the U.S. Dept. of E
Steven -
On Tue, Jun 10, 2008 at 02:57:33PM -0700, Steven Michalske wrote:
> Remember the high school science teacher docking points for not using
> units?
It's burned into my skull!
> What unit should we define for PCB default units?
> They are mill/100, one hundred thousandth of an inch, or
On Wed, Jun 04, 2008 at 02:04:34PM -0400, Stuart Brorson wrote:
> Just out of curiosity, who is maintaining xcircuit? Is it Tim
> Edwards? Is it under active development, or static?
I use 3.6.130, released February 5, 2008 at 2:40am.
I now see 3.6.131, released May 16, 2008 at 2:40am:
Changed
Peter -
On Wed, Jun 04, 2008 at 06:41:25PM +0100, Peter TB Brett wrote:
> On Wednesday 04 June 2008 17:30:11 Larry Doolittle wrote:
> >
> > Churn in file formats and user interface. I know other people
> > label this as progress, but it does keep me from advocating gED
Sorry to tack on to another response.
On Wed, Jun 04, 2008 at 01:15:24PM -0300, John Coppens wrote:
> On Wed, 4 Jun 2008 09:55:26 + (UTC)
> Kai-Martin Knaak <[EMAIL PROTECTED]> wrote:
> > * What OS do you run geda applications on?
Debian, Ubuntu, x86 and amd64.
> > * How did you install your
On Tue, Jun 03, 2008 at 02:09:34AM +0400, [EMAIL PROTECTED] wrote:
> I've started with free Xilinx ISE, but now i'm trying to do my best to
> take part in icarus verilog community.
Welcome!
> iverilog -tfpga test.v
> test.v:7: sorry: Forgot to implement NetCondit::synth_sync
> test.v:6: error: Un
Gene -
On Wed, May 21, 2008 at 06:47:38PM +, [EMAIL PROTECTED] wrote:
> How are you running lint? The only linter I've spent time with, is splint
> and never figured out, how to apply it to verilog. Recently, Aldec has added
> a linter to their product line. If you don't mind the cost, it
I just finished cleaning out some lint on some Verilog code
and infrastructure, and thought it might be nice to share some
of my techniques.
Context is Icarus Verilog, gtkwave, and running regression-style
testbenches on production synthesizable FPGA code.
Suppose we have a synthesizable foo.v, t
On Thu, May 15, 2008 at 11:52:58AM +0100, Farrukh Aslam wrote:
> > My last big project had something like 900 rats and I routed them all by
> > hand...
> By hand-routing I mean selecting the 'line' option and drawing the
> whole route from pin to pin. Or is there any smarter way ?
That's it. The
On Wed, May 14, 2008 at 01:28:24PM -0700, Ben Jackson wrote:
> On Wed, May 14, 2008 at 09:16:02PM +0100, Farrukh Aslam wrote:
> >
> > In my pcb layout, the 'auto-route' option replaces about half the rats
> > lines by traces. Do I have to route all the other rats lines manually
> > or is there any
Evan -
On Thu, May 08, 2008 at 06:41:39PM +0100, Evan Lavelle wrote:
> I can't run configure after downloading from git and sourcing
> autoconf.sh. The output from configure ends with:
>
> checking for BZ2_bzdopen in -lbz2... yes
> checking for BZ2_bzdopen in -lbz2... (cached) yes
> ../../git2/v
On Fri, May 02, 2008 at 01:06:47PM -0400, Ian Chapman wrote:
> Crystal usually cut to + or - 100 ppm for a general use like a CPU and it
> will not change too much with temperature and age. Ethernet crystals were
> at one time cut to a better spec 50 ppm. Special communications crystal can
> be a
Randall -
On Fri, May 02, 2008 at 12:33:03PM -0400, Randall Nortman wrote:
> Just a quick non-gEDA design question -- I have the choice between
> using the zero crossings of the 60Hz mains voltage or my MCU clock
> (generated from an 18.432MHz quartz crystal producing a 48MHz CPU
> clock via PLL b
On Sun, Apr 13, 2008 at 06:45:17PM -0400, Ormund Williams wrote:
> On Sun, 2008-04-13 at 17:53 -0400, Dan McMahill wrote:
> > ok, it was easier to find than I thought. google for 'pads-d2x' and
> > you'll find a post to this list from our very own Larry Doolittle.
Steve -
On Fri, Mar 28, 2008 at 10:27:28AM -0700, Steve Meier wrote:
> On Fri, 2008-03-28 at 10:20 -0700, Larry Doolittle wrote:
> > OK. Just be sure to give the FPGA direct access (via PHY) to
> > Ethernet. The same concept also applies to network performance.
> > I'
Steve -
On Fri, Mar 28, 2008 at 10:10:27AM -0700, Steve Meier wrote:
> High speed memory is now staggering the transmission of each data line
> to minimize cross talk. High end fpga's can support qdr II memory
> devices to clock speeds of over 500 MHz. The qdr ii has two data buses
> one for read
On Thu, Mar 27, 2008 at 10:29:02PM -0700, Larry Doolittle wrote:
> This question has a long history. Perhaps the most notable
> discussion is the 173-long thread titled "FPGA openness" in
> 2000 in comp.arch.fpga.
BTW, I'm particulary pleased with Rickman's post
h
Jesse -
On Thu, Mar 27, 2008 at 08:28:29PM -0700, Jesse Gordon wrote:
> Igor2 wrote:
> > If we are at tools, I wonder... Is there an FPGA family that I could use
> > without using non-free software at all?
> >
> I was going to ask that very question. The closest I've come to "free"
> was xilin
1 - 100 of 146 matches
Mail list logo
