+(define_insn "*aarch64_bfxil"
+ [(set (match_operand:GPI 0 "register_operand" "=r,r")
+(ior:GPI (and:GPI (match_operand:GPI 1 "register_operand" "r,0")
+ (match_operand:GPI 3 "const_int_operand" "n, Ulc"))
+ (and:GPI (match_operand:GPI 2 "register_operand" "0,r")
Hi Jeff,
On 06/29/2018 08:34 PM, Jeff Law wrote:
On 03/22/2018 05:56 AM, Renlin Li wrote:
Hi all,
As described in PR84877. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84877
The local copy of parameter on stack is not aligned.
For BLKmode paramters, a local copy on the stack will be saved
Hello all,
This patch will replace all explicit calls to gen_rtx_PLUS and GEN_INT
with plus_constant.
This has been tested for aarch64-none-elf on the model.
OK for trunk?
Kind regards,
Renlin Li
gcc/ChangeLog:
2013-09-20 Renlin Li
* config/aarch64/aarch64.c
Hello all,
This patch will replace all explicit calls to gen_rtx_PLUS and GEN_INT
with plus_constant.
This has been tested for arm-none-linux-gnueabi on the model.
OK for trunk?
Kind regards,
Renlin Li
gcc/ChangeLog:
2013-09-20 Renlin Li
* config/arm/arm.c
Thank you, can you please commit it for me?
Kind regards,
Renlin Li
On 09/20/13 15:26, Marcus Shawcroft wrote:
On 20 September 2013 15:18, Renlin Li wrote:
2013-09-20 Renlin Li
* config/aarch64/aarch64.c (aarch64_expand_prologue): Use plus_constant.
(aarch64_expand_epilogue
Hello all,
Sorry for my last patch that cause some test regressions. I have correct
it, and it has been tested for aarch64-none-elf on the model.
This patch will replace all explicit calls to gen_rtx_PLUS and GEN_INT
with plus_constant.
OK for trunk?
Kind regards,
Renlin Li
gcc/ChangeLog
Hello all,
Sorry for my last patch that cause some test regressions. I have correct
it, and it has been tested for arm-none-eabi on the model.
This patch will replace all explicit calls to gen_rtx_PLUS and GEN_INT
with plus_constant.
OK for trunk?
Kind regards,
Renlin Li
gcc/ChangeLog
Hi all,
This patch will change tune_params for armv8-a architecture to general
cortex.
Change has been tested for arm-none-eabi on the model.
Ok for trunk?
Kind regards,
Renlin Li
gcc/ChangeLog:
2013-10-03 Renlin Li
* config/arm/arm-cores.def (cortex-a53): Use cortex tunning.diff
th local change.
So a simple change is made in this patch. The output operand is reloaded only
when it's not a scratch operand and it's not unused since then.
aarch64-none-linux-gnu bootstrap and regression test OK.
x86_64-linux bootstrap and regression test OK.
OK for trunk?
Regards,
Hi Richard,
On 26/02/16 12:57, Richard Biener wrote:
On Fri, Feb 26, 2016 at 1:54 PM, Renlin Li wrote:
I have checked, x86, arm, aarch64, mips, arc all have such patterns. But
it's
not triggered. In my case, it's triggered by compiling glibc with local
change.
Please extract
olve also a possible problem for correct scratch generation
during LRA.
I am going to work on this problem on the next week. A test case
would be a help for me.
gcc/ChangeLog:
2016-02-26 Renlin Li
* lra-constraints.c (curr_insn_transform): Don't generate reload for
output
this patch, -shared option is replace by -r -nostdlib. So that the standard
system startup files or libraries are not used when linking.
arm-none-eabi, aarch64-none-elf regression test OK, OK for trunk?
Regards,
Renlin Li
gcc/testsuite/ChangeLog:
2016-02-29 Renlin Li
* gcc.dg/lto/pr54709
Hi Richard,
On 01/03/16 09:16, Richard Biener wrote:
On Mon, Feb 29, 2016 at 5:13 PM, Renlin Li wrote:
Hi all,
The gcc.dg/lto/pr54709, pr61526, pr64415 linking testcases keep failing on
arm/aarch64 bare-metal target.
It's because statically built newlib library is used to link with s
Hi Richard,
On 02/03/16 13:35, Richard Biener wrote:
On Tue, Mar 1, 2016 at 4:56 PM, Renlin Li wrote:
Hi Richard,
On 01/03/16 09:16, Richard Biener wrote:
On Mon, Feb 29, 2016 at 5:13 PM, Renlin Li wrote:
Hi all,
The gcc.dg/lto/pr54709, pr61526, pr64415 linking testcases keep failing
on
Hi Richard,
On 03/03/16 10:13, Richard Biener wrote:
On Wed, Mar 2, 2016 at 5:12 PM, Renlin Li wrote:
Hi Richard,
On 02/03/16 13:35, Richard Biener wrote:
On Tue, Mar 1, 2016 at 4:56 PM, Renlin Li wrote:
Hi Richard,
On 01/03/16 09:16, Richard Biener wrote:
On Mon, Feb 29, 2016 at 5:13
Hi Richard,
On 03/03/16 12:47, Richard Biener wrote:
On Thu, Mar 3, 2016 at 1:07 PM, Renlin Li wrote:
Hi Richard,
On 03/03/16 10:13, Richard Biener wrote:
On Wed, Mar 2, 2016 at 5:12 PM, Renlin Li wrote:
Hi Richard,
On 02/03/16 13:35, Richard Biener wrote:
On Tue, Mar 1, 2016 at 4:56
Hi Ramana/Richard,
Could you please help to review this patch?
Thanks in advance!
Kind regards,
Renlin Li
On 20/11/13 16:27, Renlin Li wrote:
Hi all,
This patch will make the arm back-end use vcvt for float to fixed
point conversions when applicable.
Test on arm-none-linux-gnueabi has
defined
with additional extensions (e.g. __ARM_ARCH_EXT_IDIV__) when arch is set
to armv7ve.
Okay for trunk?
Regards,
Renlin Li
gcc/ChangeLog:
2013-12-20 Renlin Li
* config.gcc: Add armv7ve for --with-arch option.
* config/arm/arm-arches.def (ARM_ARCH): Add armv7ve arch
Hi,
I just updated my patch according your suggestion.
Thank you for committing it for me!
All you guys have a nice Xmas break!
Kind regards,
Renlin Li
On 04/12/13 11:23, Ramana Radhakrishnan wrote:
Sorry about the slow response. Been on holiday.
On 20/11/13 16:27, Renlin Li wrote:
Hi all
test case and a patch
is on the way.
Thank you for your notification!
Kind regards,
Renlin Li
On 08/01/14 16:43, Christophe Lyon wrote:
Hi Renlin,
The new test you added introduces 2 new FAILs when the target is
arm-none-linux-gnueabi (as opposed to arm-none-linux-gnueabihf).
Christophe
Hi Gerald,
Sorry for the late reply!
We're working on a list of all the ARM-related changes in 4.9. This will
also be included.
Kind regards,
Renlin
On 03/01/14 13:24, Gerald Pfeifer wrote:
Renlin Li wrote:
Hi all,
This patch will add armv7ve support to gcc. Armv7ve is basically a
?
Regards,
Renlin Li
diff --git a/gcc/testsuite/gcc.dg/pr44194-1.c b/gcc/testsuite/gcc.dg/pr44194-1.c
index 0182f75..8899500 100644
--- a/gcc/testsuite/gcc.dg/pr44194-1.c
+++ b/gcc/testsuite/gcc.dg/pr44194-1.c
@@ -15,5 +15,5 @@ void func() {
/* { dg-final { scan-rtl-dump "global deletions
Hi Eric,
Thank you for your suggestion!
I have made the adjustment and test it. Please check the new attachment.
Regards,
Renlin Li
On 10/01/14 10:42, Eric Botcazou wrote:
This patch will resolve testsuite/gcc.dg/pr44194-1.c failure observed in
aarch64 target by refining the second scan-rtl
Hi Vladimir,
I have test your patch with the following configurations, , and it
indeed eliminates the ICE.
--target=arm-none-linux-gnueabihf
--with-arch=armv7-a
--with-fpu=vfpv3-d16
--with-float=softfp
Thank you!
Kind regards,
Renlin Li
On 14/01/14 16:48, Vladimir Makarov wrote:
The
Hi Jeff,
Thank you for the suggestion! I will committed it first and continue
working on it.
Regards,
Renlin Li
On 08/07/15 21:56, Jeff Law wrote:
On 07/08/2015 09:03 AM, Renlin Li wrote:
Hi all,
In simplify_const_relational_operation function, there are cases a const
rtx
will be returned
to commit?
gcc/testsuite/ChangeLog:
2015-07-28 Renlin Li
* gcc.target/aarch64/arm_align_max_pwr.c: Make it a compile test case,
check the assembly.
* gcc.target/aarch64/arm_align_max_stack_pwr.c: Likewise.
diff --git a/gcc/testsuite/gcc.target/aarch64/arm_align_max_pwr.c b/gcc
])
(const_int 0 [0]))
(zero_extend:SI (reg:QI 1 x1 [ y ])))
aarch64-none-elf regression tests Okay. Okay to commit?
Regards,
Renlin
gcc/ChangeLog:
2015-07-30 Renlin Li
* config/aarch64/aarch64.md (combine_bfi): New pattern.
gcc/testsuite/ChangeLog:
2015-07-30 Renlin Li
* gcc.target
Hi Uros,
You seems committing the test case in the wrong directory. I found it
in testsuite/gcc.target/pr66648.c.
Regards,
Renlin
On Sat, Jul 25, 2015 at 10:23 AM, Uros Bizjak wrote:
> We have to emit check for main loop execution UNLESS we guarantee that
> min_size is at least equal to size_ne
Hi Kyrill,
On 30/07/15 17:08, Kyrill Tkachov wrote:
Hi Renlin,
On 30/07/15 16:50, Renlin Li wrote:
Hi all,
This insn should match the following similar rtx pattern and remove the
redundant zero_extend operation if the width of zero_extract and
inner-size of zero_extend totally match.
(set
, wzr
cselx0, x2, x1, eq
ret
Without the path, the old code-generation is like this:
uxtwx1, w1
cmp w0, wzr
uxtwx2, w2
cselx0, x2, x1, eq
ret
aarch64-none-elf regression test Okay. Okay to commit?
Regards,
Renlin Li
gcc
Hi Pinski,
On 06/08/15 10:48, pins...@gmail.com wrote:
On Aug 6, 2015, at 11:40 AM, Renlin Li wrote:
Hi all,
This is a simple patch to add a new cmovdi_insn_uxtw rtx pattern to aarch64
backend.
For the following simple test case:
unsigned long
foo (unsigned int a, unsigned int b
w0, wzr
cselw0, w1, w2, ne
ret
Without the path, the old code-generation is like this:
uxtwx2, w2
uxtwx1, w1
cmp w0, wzr
cselx0, x2, x1, eq
ret
aarch64-none-elf regression test Okay. Okay to commit?
Regards,
Renlin Li
gcc
commit?
Regards,
Renlin Li
gcc/ChangeLog:
2015-10-02 Renlin Li
* config/aarch64/aarch64.md (csneg3_uxtw_insn): New pattern.
gcc/testsuite/ChangeLog:
2015-10-02 Renlin Li
* gcc.target/aarch64/csneg-1.c: Update test.
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64
Hi Jeff,
Your patch causes an ICE regression.
The test case is " gcc.c-torture/compile/pr27087.c", I observed it on
aarch64-none-elf target when compiling the test case with '-Os' flag.
A quick check shows, the cfg has been changed, but the loop information
is not updated. Thus the informatio
arm-none-linux-gnueabihf regression tests Okay. Okay to commit?
Regards,
Renlin Li
gcc/ChangeLog:
2015-10-06 Renlin Li
* config/arm/neon.md (neon_vuzp_insn): Add & modifier for
operands[0] and operands[2].
(neon_vtrn_insn): Likewise.
(neon_vzip_insn): Likewise.
rt to 4.9?
Regards,
Renlin Li
gcc/ChangeLog:
2015-10-15 Renlin Li
PR target/67383
Backport from mainline.
2014-04-22 Ramana Radhakrishnan
* config/arm/arm.c (arm_hard_regno_mode_ok): Loosen
restrictions on core registers for DImode values in Thumb2.
Hi Ramana,
On 16/10/15 11:52, Ramana Radhakrishnan wrote:
On Thu, Oct 15, 2015 at 03:01:24PM +0100, Renlin Li wrote:
Hi all,
This is a backport patch to loosen restrictions on core registers
for DImode values in Thumb2.
It fixes PR67383. In this particular case, reload tries to spill a
hard
ck.
Okay to commit on the trunk?
Regards,
Renlin Li
gcc/testsuite/ChangeLog:
2015-10-26 Renlin Li
* lib/target-supports.exp (check_effective_target_freorder): Add
-fprofile-use flag.
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
ind
On 26/10/15 13:24, Bernd Schmidt wrote:
On 10/26/2015 02:17 PM, Teresa Johnson wrote:
On Mon, Oct 26, 2015 at 2:00 AM, Renlin Li wrote:
* lib/target-supports.exp (check_effective_target_freorder): Add
-fprofile-use flag.
Hmmm, the testcases themselves which use this predicate
Hi Jason,
On 08/10/15 03:42, Jason Merrill wrote:
While looking at another issue I noticed that in g++.dg/init/vbase1.C
the Diamond(int) constructor was unnecessarily storing a CONSTRUCTOR
into a stack temporary and then copying it into the SubB base
subobject rather than directly storing the
end:TF (reg:DI 2 x2 [ __x+-8 ])))
/libstdc++-v3/include/complex:861 689 {aarch64_movtfhigh_di}
(nil))
Regards,
Renlin Li
On 29/10/15 16:33, Richard Biener wrote:
On October 29, 2015 4:37:08 PM GMT+01:00, Ramana Radhakrishnan
wrote:
On Thu, Jun 4, 2015 at 2:16 PM, Renlin Li wrote:
Ping ~
C
rt to branch 5 and 4.9?
Regards,
Renlin Li
gcc/ChangeLog:
2015-11-12 Renlin Li
* config/arm/arm.md (addsi3_compare_op2): Make the order of
assembly pattern consistent with constraint order.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 8ebb1bf..73c3088 100644
---
.
This passes for aarch64 and mips as they have zero register to do that.
However, other RISC might not have that feature, for example arm and
RS6000 in this case.
https://gcc.gnu.org/ml/gcc-patches/2015-10/msg03239.html
Regards,
Renlin Li
Dollar sign is not a valid identifier on AIX, so g
Hi Ramana,
On 16/10/15 14:54, Renlin Li wrote:
The command line implies we remove r7 (frame pointer in Thumb2 -
historical accident, fno-omit-frame-pointer), r9 (ffixed-r9), r10
(-mpic-register) which
leaves us with:
* r0, r1
* r2, r3
* r4, r5
as the only free registers available for
rch64-none-elf regression test Okay. Okay to check in?
gcc/ChangeLog:
2017-06-06 Renlin Li
PR target/63359
* config/aarch64/aarch64.c (aarch64_print_operand): Add 'r' modifier.
* doc/extend.texi (AArch64Operandmodifiers): New section.
commit f8725ffd1375a8347c
171.swim fails on aarch64-linux as well. I dis a bisect and confirm it's r248877 causing
the miscompare.
Regards,
Renlin
On 06/06/17 12:05, Markus Trippelsdorf wrote:
On 2017.06.05 at 22:39 +0200, Nicolas Koenig wrote:
With all the style fixes committed as r248877.
171_swim fails now. I did
Ping ~
On 14/12/16 15:33, Renlin Li wrote:
Ping~
Regards,
Renlin
On 16/06/16 12:04, Renlin Li wrote:
Hi all,
GCC has startfile and endfile spec string built into it.
startfile is used to specify objects files to include at the start of the link
process.
While endfile, on the other hand, is
alls option.
This patch changes the dump_stack function call conditional, which fixes the
regression.
Okay to commit?
Regards,
Renlin
gcc/testsuite/ChangeLog:
2017-06-12 Renlin Li
* gcc.target/arm/cold-lc.c: Update coding style, call dump_stack
conditionally.
On 09/06/17 10:54,
Hi Martin,
On 04/06/17 23:24, Martin Sebor wrote:
On 06/02/2017 09:38 AM, Renlin Li wrote:
Hi Martin,
After r247444, I saw the following two regressions in
arm-linux-gnueabihf environment:
FAIL: gcc.dg/tree-ssa/builtin-sprintf-warn-18.c (test for warnings,
line 119)
PASS: gcc.dg/tree-ssa
ncated to LONG_MAX (in target_strtol10 function)
I have checked in cross build environment (host x86_64), this variable is true.
Regards,
Renlin
On 13/06/17 09:16, Renlin Li wrote:
Hi Martin,
On 04/06/17 23:24, Martin Sebor wrote:
On 06/02/2017 09:38 AM, Renlin Li wrote:
Hi Martin,
After r247444, I
library one.
So that memcpy won't be called accidentally.
Okay to commit?
gcc/testsuite/ChangeLog:
2017-06-22 Renlin Li
Szabolcs Nagy
* gcc.c-torture/execute/builtins/memops-asm-lib.c (my_memmove): New.
* gcc.c-torture/execute/builtins/memops-asm.c (me
Hi Martin,
On 23/06/17 16:27, Martin Sebor wrote:
On 06/23/2017 03:19 AM, Renlin Li wrote:
Hi all,
After the change r249278. bcopy is folded into memmove. And in newlib
aarch64
memmove implementation, it will call memcpy in certain conditions.
The memcpy defined in memops-asm-lib.c will abort
Hi Andrew,
On 25/06/17 22:38, Andrew Pinski wrote:
On Tue, Jun 6, 2017 at 3:56 AM, Renlin Li wrote:
Hi all,
In this patch, a new integer register operand modifier 'r' is added. This
will use the
proper register name according to the mode of corresponding operand.
'w'
Hi Andrew,
On 27/06/17 17:11, Andrew Pinski wrote:
On Tue, Jun 27, 2017 at 8:27 AM, Renlin Li wrote:
Hi Andrew,
On 25/06/17 22:38, Andrew Pinski wrote:
On Tue, Jun 6, 2017 at 3:56 AM, Renlin Li wrote:
Hi all,
In this patch, a new integer register operand modifier 'r' is a
ffects gcc-6, gcc-7 as well. Backport are needed for those
branches.
Regards,
Renlin
gcc/ChangeLog:
2017-12-11 Renlin Li
PR target/83370
* config/aarch64/aarch64.c (aarch64_class_max_nregs): Handle
TAILCALL_ADDR_REGS.
(aarch64_register_move_cost)
Ping ~
On 11/12/17 15:27, Renlin Li wrote:
Hi all,
In aarch64 backend, ip0/ip1 register will be used in the prologue/epilogue as
temporary register.
When the compiler is performing sibcall optimization. It has the chance to use
ip0/ip1 register for indirect function call to hold the address
-elf regression test Okay without regressions.
Okay to commit?
Regards,
Renlin
gcc/ChangeLog:
2018-01-03 Renlin Li
* config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Make
sure address is Pmode.
* config/aarch64/aarch64.md (ldr_got_small): Fix address mode
add x0, sp, 16
str x0, [sp, 8]
mov x0, x16
mov x16, 20016
add sp, sp, x16
br x0
I updated the patch with the new test case,
the wording about the register constraint is also updated.
Thanks,
Renlin
gcc/ChangeLog:
2018-01-30
to commit?
Regards,
Renlin
gcc/ChangeLog:
2018-01-31 Renlin Li
* gimple-ssa-sprintf.c (target_strtol10): Use target integer to check
the range. Rename it into
(target_strtoi10): This.
(parse_directive): Compare with target int max instead of LONG_MAX.
Hi Martin,
On 01/02/18 00:40, Martin Sebor wrote:
On 01/31/2018 10:36 AM, Renlin Li wrote:
Hi there,
I have a patch to fix to regressions we observed in armhf native
environment.
To effectively check out of range for format string, a target type
should be
used. And according to the standard
Hi James,
Thanks for the review! I committed it on trunk.
Is it Okay to backport this patch to release branch 5, 6,7?
It applies cleanly without any logic changes.
Regards,
Renlin
On 31/01/18 17:56, James Greenhalgh wrote:
On Tue, Jan 30, 2018 at 03:45:17PM +, Renlin Li wrote:
Hi
to commit the patch?
Regards,
Renlin
gcc/ChangeLog:
2018-03-07 Renlin Li
* config/aarch64/aarch64.md (movhf_aarch64): Fix mode argument to
aarch64_output_scalar_simd_mov_immediate.
gcc/testsuite/ChangeLog:
2018-03-07 Renlin Li
* gcc.target/aarch64/movi_hf.c: New
by value.
x86-linux, arm-none-eabi, aarch64-one-elf regression test Okay.
linux-armhf bootstrap Okay.
I assume there are other targets which will be affected by the change.
But I don't have environment to test.
Okay the commit?
Regards,
Renlin
gcc/
2018-03-22 Renlin Li
Hi H.J.
On 22/03/18 12:55, H.J. Lu wrote:
On Thu, Mar 22, 2018 at 5:52 AM, H.J. Lu wrote:
On Thu, Mar 22, 2018 at 4:56 AM, Renlin Li wrote:
Hi all,
As described in PR84877. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84877
The local copy of parameter on stack is not aligned.
For BLKmode
(or address?).
Okay to commit?
Regards,
Renlin
gcc/ChangeLog:
2018-03-23 Renlin Li
* tree.def (ADDR_EXPR): Correct the commnet.
diff --git a/gcc/tree.def b/gcc/tree.def
index 31de6c0994de43c175b924d4ba578a131fb4d524..1e5aca811f801c54be9215a9d86028f50a4ec608 100644
--- a/gcc/tree.def
Hi Jeff,
On 23/03/18 23:19, Jeff Law wrote:
On 03/23/2018 09:44 AM, Renlin Li wrote:
Hi all,
This is a simple patch to correct the comment for ADDR_EXPR tree code.
The resulting expression of ADDR_EXPR is a tree with POINTER_TYPE.
So the result mode should ptr_mode instead of Pmode.
As far
Hi Martin,
pr82625.C failed on compiler builds which don't support "default" and "avx"
target.
For example, arm/aarch64 native linux gcc compiler.
As I found in this gcc wiki: https://gcc.gnu.org/wiki/FunctionMultiVersioning
'''
This support is available in GCC 4.8 and later. Support is only a
-march=armv7ve option is
presented.
.arch armv7-a
.arch_extension idiv
.arch_extension mp
.arch_extension sec
.arch_extension virt
Okay for trunk?
gcc/ChangeLog:
2013-11-12 Renlin Li
* config.gcc: Add armv7ve for --with-arch option.
* config/arm/arm-arches.def (ARM_ARCH): Add armv7ve
Hi all,
This patch will make the arm back-end use vcvt for float to fixed point
conversions when applicable.
Test on arm-none-linux-gnueabi has been done on the model.
Okay for trunk?
Kind regards,
Renlin Li
gcc/ChangeLog:
2013-11-20 Renlin Li
* config/arm/arm-protos.h
Hi all,
This is a simple patch to add missing __ARM_FEATURE_IDIV__ predefined
marco(ACLE 2.0) into TARGET_CPU_CPP_BUILTINS.
Is it Okay to commit?
gcc/ChangeLog:
2014-10-13 Renlin Li
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Add ACLE 2.0 predefined
marco __ARM_FEATURE_IDIV__
Hi all,
This is a simple patch to remove unused variables and marco.
Is it Okay to commit?
gcc/ChangeLog:
2014-10-13 Renlin Li
* config/aarch64/aarch64.h (ARM_DEFAULT_PCS, arm_pcs_variant): Delete.
Regards,
Renlin LiFrom 88b6dc7fccf70c140070fbc5472d9bc1a8590754 Mon Sep 17 00:00:00
Hi all,
This patch is part of a series of patches that implement ACLE 2.0
predefined macro support for AArch64.
aarch64-none-elf target has been tested on the model, no regression.
Is it Okay to commit?
Kind regards!
Renlin Li
gcc/ChangeLog:
2014-10-15 Renlin Li
* config/aarch64
Hi all,
This patch is part of a series of patches that implement ACLE 2.0
predefined macros support for AArch64.
aarch64-none-elf target has been tested on the model, no regression.
Is it Okay to commit?
Kind regards!
Renlin Li
gcc/ChangeLog:
2014-10-15 Renlin Li
* config/aarch64
Hi all,
This patch is part of a series of patches that implement ACLE 2.0
predefined macros support for AArch64.
aarch64-none-elf target has been tested on the model, no regression.
Is it Okay to commit?
Kind regards!
Renlin Li
gcc/ChangeLog:
2014-10-15 Renlin Li
* config/aarch64
Are you sure that the ACLE documents this with trailing underscores ?
The copy that I have doesn't.
You are right, it's my incaution. I have double checked, the macro
should be __ARM_FEATURE_IDIV.
Could you please do a obvious fix? Thank you so much!
Kind regards,
Renlin
Ping~
Anybody can review this? Thank you!
Regards,
Renlin Li
On 06/05/15 09:09, Renlin Li wrote:
Hi all,
This is a simple patch to add _GLIBCXX_HAVE_LIMIT_FSIZE to guard the
test.
In libstdc++-v3/testsuite/util/testsuite_hooks.cc. set_file_limit()
function is nullified when either
Is it Okay for me to backport it to gcc-5?
Regards,
Renlin Li
On 30/04/15 16:21, Marcus Shawcroft wrote:
On 30 April 2015 at 12:55, Renlin Li wrote:
2015-04-30 Renlin Li
* config/aarch64/aarch64-simd.md (vec_shr): Defined as an unspec.
* config/aarch64/iterators.md (unspec
maximum alignment allowed by GCC(without producing "error:
requested alignment is too large"), "int" will overflow.
Okay to Commit on the trunk and backport to branch 5.0?
Regards,
Renlin Li
gcc/ChangeLog:
2015-06-04 Renlin Li
* varasm.c (emit_local): Use unsigne
Ping ~
Can somebody review it? Thank you!
Regards,
Renlin Li
On 16/04/15 10:32, Renlin Li wrote:
Ping~
Regards,
Renlin Li
On 16/04/15 10:09, wrote:
Ping~
Anybody has time to review it?
Regards,
Renlin Li
On 06/02/15 17:48, Renlin Li wrote:
Hi all,
This is a backport patch for branch
On 29/04/15 11:58, Marcus Shawcroft wrote:
On 29 April 2015 at 01:24, Andrew Pinski wrote:
On Tue, Dec 16, 2014 at 2:19 AM, Renlin Li wrote:
Hi all,
This is a simple patch to add another two ACLE 2.0 predefined macros into
aarch64 backend.
They are __ARM_ALIGN_MAX_PWR and
Hi Jonathan,
I have committed it on trunk.
Is it Okay for me to backport it to branch 5.0, 4.9 to remove failing noise?
Regards,
Renlin Li
On 01/06/15 16:58, Jonathan Wakely wrote:
On 06/05/15 09:09 +0100, Renlin Li wrote:
Hi all,
This is a simple patch to add _GLIBCXX_HAVE_LIMIT_FSIZE to
Ping~
Regards,
Renlin Li
On 16/04/15 10:09, wrote:
Ping~
Anybody has time to review it?
Regards,
Renlin Li
On 06/02/15 17:48, Renlin Li wrote:
Hi all,
This is a backport patch for branch 4.9. You can find the original=20
patch here:https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00356.html
xpanded as
expand_mem_thread_fence (MEMMODEL_SEQ_CST).
Okay to commit?
libstdc++-v3/ChangeLog:
2015-04-21 Renlin Li
* testsuite/lib/dg-options.exp (dg-require-thread-fence): New.
* testsuite/lib/libstdc++.exp (check_v3_target_thread_fence): New.
* testsuite/29_atomics/atomic_flag/clear
Hi all,
This is a simple patch to generate a move instruction to temporarily
hold the large immediate for a add instruction.
GCC regression test has been run using aarch64-none-elf toolchain. NO
new issues.
Okay for trunk?
Regards,
Renlin Li
gcc/ChangeLog:
2015-04-21 Renlin Li
Hi Jonathan,
Thank you for the suggestion. I have just attached the updated the
patch. It works as before.
Is this Okay to commit?
Regards,
Renlin Li
On 22/04/15 11:19, Jonathan Wakely wrote:
On 21/04/15 15:29 +0100, Renlin Li wrote:
Hi all,
This patch defines a new dg-require-thread
nd it passes on both aarch64-none-elf and
aarch64_be-none-elf tool-chain.
Okay to commit?
Regards,
Renlin Li
gcc/ChangeLog:
2015-04-28 Renlin Li
* config/aarch64/aarch64-simd.md (vec_shr_): Use shl.
gcc/testsuite/ChangeLog:
2015-04-28 Renlin Li
Ping~
Regards,
Renlin Li
On 16/12/14 10:19, Renlin Li wrote:
Hi all,
This is a simple patch to add another two ACLE 2.0 predefined macros
into aarch64 backend.
They are __ARM_ALIGN_MAX_PWR and __ARM_ALIGN_MAX_STACK_PWR. Currently,
those two values are hard-wired to 16.
The following clauses
Ping~
Regards,
Renlin Li
On 16/04/15 10:32, Renlin Li wrote:
Ping~
Regards,
Renlin Li
On 16/04/15 10:09, wrote:
Ping~
Anybody has time to review it?
Regards,
Renlin Li
On 06/02/15 17:48, Renlin Li wrote:
Hi all,
This is a backport patch for branch 4.9. You can find the original
patch
are right. This pattern has ambiguity. I have updated the patch, and
represent vec_shr as an upspec. This will prevent other rtx patterns
implicitly matching this one.
The new patch is attached, is it Okay to commit?
Regards,
Renlin Li
gcc/ChangeLog:
2015-04-30 Renlin Li
* config/aarc
Hi all,
The new test case requires the target to support atomic operations on
"int" type. By adding the correct target selector, it fixes the
regression on arm-none-elf target.
Okay to commit?
gcc/testsuite/ChangeLog:
2015-05-01 Renlin Li
* gcc.dg/pr65345-2.c: Add syn
Hi Marcus,
On 01/05/15 11:19, Marcus Shawcroft wrote:
On 21 April 2015 at 17:10, Renlin Li wrote:
Hi all,
This is a simple patch to generate a move instruction to temporarily hold
the large immediate for a add instruction.
GCC regression test has been run using aarch64-none-elf toolchain
_GLIBCXX_RES_LIMITS, however,
_GLIBCXX_HAVE_LIMIT_FSIZE is not checked.
The complete condition for correct execution of this test case is that,
those two macros are both defined.
Is Okay to commit?
Regards,
Renlin Li
libstdc++-v3/ChangeLog:
2015-05-06 Renlin Li
* testsuite/27_io/fpos/14775.cc: Add
Hi Jonathan,
On 22/04/15 13:58, Jonathan Wakely wrote:
On 22 April 2015 at 12:25, Renlin Li wrote:
Hi Jonathan,
Thank you for the suggestion. I have just attached the updated the patch. It
works as before.
Is this Okay to commit?
OK, thanks.
Is it Okay for me to backport this patch to
Hi all,
This is a simple patch to add more conditional macros defined ACLE 2.0.
aarch64-none-elf target is tested on the model, no new issues.
Is this Okay for trunk?
gcc/ChangeLog:
2014-11-17 Renlin Li
* config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Define
__ARM_FP_FAST
problem.
A testcase is added for all targets as I think it's a middle-end issue.
And sorry for not being able to simplify it.
arm-none-eabi has been test on the model, no new issues. bootstrapping
and regression tested on x86, no new issues.
Is it Okay to commit?
gcc/ChangeLog:
20
On 10/11/14 16:55, Renlin Li wrote:
On 06/11/14 15:00, Renlin Li wrote:
Hi all,
Dose anybody have time to review this?
Kind regards,
Renlin Li
On 31/10/14 14:51, Renlin Li wrote:
Hi all,
This is a patch which will fix PR63424.
It implements signed/unsigned max/min pattern for V2DI mode in
patch shortly.
Regards,
Renlin Li
On 19/11/14 11:20, Richard Henderson wrote:
On 10/31/2014 03:51 PM, Renlin Li wrote:
+(define_expand "v2di3"
+ [(parallel [
+(set (match_operand:V2DI 0 "register_operand" "")
+(MAXMIN:V2DI (match_operand:V2DI 1 "register_operand" &qu
ted on x86, no new issues.
Is it Okay for gcc-4_9-branch?
gcc/ChangeLog:
2014-11-20 Renlin Li
PR middle-end/63762
* ira.c (ira): Update preferred class.
gcc/testsuite/ChangeLog:
2014-11-20 Renlin Li
PR middle-end/63762
* gcc.dg/pr63762.c: New.diff --git a/gcc/ira.c b
Hi,
This patch is to add myself into section of
MAINTAINERS file.
Is it Okay to commit?
Regards,
Renlin Li
ChangeLog:
2014-11-21 Renlin Li
* MAINTAINERS (Write After Approval): Add myself.diff --git a/MAINTAINERS b/MAINTAINERS
index 56e68c5..96a7497 100644
--- a/MAINTAINERS
+++ b
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