Hi,
I just updated my patch according your suggestion.
Thank you for committing it for me!
All you guys have a nice Xmas break!
Kind regards,
Renlin Li
On 04/12/13 11:23, Ramana Radhakrishnan wrote:
Sorry about the slow response. Been on holiday.
On 20/11/13 16:27, Renlin Li wrote:
Hi all,
This patch will make the arm back-end use vcvt for float to fixed point
conversions when applicable.
Test on arm-none-linux-gnueabi has been done on the model.
Okay for trunk?
+ (define_insn "*combine_vcvtf2i"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (fix:SI (fix:SF (mult:SF (match_operand:SF 1 "s_register_operand" "t")
+ (match_operand 2
+ "const_double_vcvt_power_of_two" "Dp")))))]
+ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
+ "vcvt%?.s32.f32\\t%1, %1, %v2\;vmov%?\\t%0, %1"
+ [(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
+ (set_attr "ce_count" "2")
+ (set_attr "type" "f_cvtf2i")]
+ )
+
You need to set length to 8.
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/fixed_float_conversion.c
@@ -0,0 +1,15 @@
+/* Check that vcvt is used for fixed and float data conversions. */
+/* { dg-do compile } */
+/* { dg-options "-O1 -mfpu=vfp3" } */
+/* { dg-require-effective-target arm_vfp_ok } */
+float fixed_to_float(int i)
+{
+ return ((float)i / (1 << 16));
+}
+
+int float_to_fixed(float f)
+{
+ return ((int)(f*(1 << 16)));
+}
+/* { dg-final { scan-assembler "vcvt.f32.s32" } } */
+/* { dg-final { scan-assembler "vcvt.s32.f32" } } */
GNU coding style for functions.
Ok with those changes.
regards
Ramana
Kind regards,
Renlin Li
gcc/ChangeLog:
2013-11-20 Renlin Li <renlin...@arm.com>
* config/arm/arm-protos.h (vfp_const_double_for_bits): Declare.
* config/arm/constraints.md (Dp): Define new constraint.
* config/arm/predicates.md ( const_double_vcvt_power_of_two): Define
new predicate.
* config/arm/arm.c (arm_print_operand): Add print for new fucntion.
(vfp3_const_double_for_bits): New function.
* config/arm/vfp.md (combine_vcvtf2i): Define new instruction.
gcc/testsuite/ChangeLog:
2013-11-20 Renlin Li <renlin...@arm.com>
* gcc.target/arm/fixed_float_conversion.c: New test case.
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 944cf10..f2f8272 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -275,6 +275,8 @@ struct tune_params
extern const struct tune_params *current_tune;
extern int vfp3_const_double_for_fract_bits (rtx);
+/* return power of two from operand, otherwise 0. */
+extern int vfp3_const_double_for_bits (rtx);
extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx,
rtx);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 78554e8..72c4204 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -21175,7 +21175,11 @@ arm_print_operand (FILE *stream, rtx x, int code)
case 'v':
gcc_assert (CONST_DOUBLE_P (x));
- fprintf (stream, "#%d", vfp3_const_double_for_fract_bits (x));
+ int result;
+ result = vfp3_const_double_for_fract_bits (x);
+ if (result == 0)
+ result = vfp3_const_double_for_bits (x);
+ fprintf (stream, "#%d", result);
return;
/* Register specifier for vld1.16/vst1.16. Translate the S register
@@ -28958,6 +28973,26 @@ vfp3_const_double_for_fract_bits (rtx operand)
}
return 0;
}
+
+int
+vfp3_const_double_for_bits (rtx operand)
+{
+ REAL_VALUE_TYPE r0;
+
+ if (!CONST_DOUBLE_P (operand))
+ return 0;
+
+ REAL_VALUE_FROM_CONST_DOUBLE (r0, operand);
+ if (exact_real_truncate (DFmode, &r0))
+ {
+ HOST_WIDE_INT value = real_to_integer (&r0);
+ value = value & 0xffffffff;
+ if ((value != 0) && ( (value & (value - 1)) == 0))
+ return int_log2 (value);
+ }
+
+ return 0;
+}
/* Emit a memory barrier around an atomic sequence according to MODEL. */
diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md
index e2a3099..59ca4b6 100644
--- a/gcc/config/arm/constraints.md
+++ b/gcc/config/arm/constraints.md
@@ -31,7 +31,7 @@
;; 'H' was previously used for FPA.
;; The following multi-letter normal constraints have been used:
-;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, Dl, DL, Do, Dv, Dy, Di, Dt, Dz
+;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, Dl, DL, Do, Dv, Dy, Di, Dt, Dp, Dz
;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
@@ -328,12 +328,18 @@
(and (match_code "const_double")
(match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
-(define_constraint "Dt"
+(define_constraint "Dt"
"@internal
In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
(and (match_code "const_double")
(match_test "TARGET_32BIT && TARGET_VFP && vfp3_const_double_for_fract_bits (op)")))
+(define_constraint "Dp"
+ "@internal
+ In ARM/ Thumb2 a const_double which can be used with a vcvt.s32.f32 with bits operation"
+ (and (match_code "const_double")
+ (match_test "TARGET_32BIT && TARGET_VFP && vfp3_const_double_for_bits (op)")))
+
(define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS"
"For arm_restrict_it the core registers @code{r0}-@code{r7}. GENERAL_REGS otherwise.")
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index 29e1e5c..2dac581 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -639,8 +639,13 @@
(define_predicate "const_double_vcvt_power_of_two_reciprocal"
(and (match_code "const_double")
- (match_test "TARGET_32BIT && TARGET_VFP
- && vfp3_const_double_for_fract_bits (op)")))
+ (match_test "TARGET_32BIT && TARGET_VFP
+ && vfp3_const_double_for_fract_bits (op)")))
+
+(define_predicate "const_double_vcvt_power_of_two"
+ (and (match_code "const_double")
+ (match_test "TARGET_32BIT && TARGET_VFP
+ && vfp3_const_double_for_bits (op)")))
(define_predicate "neon_struct_operand"
(and (match_code "mem")
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index 6d0515a..c216dbc 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -1253,6 +1253,20 @@
(set_attr "length" "8")]
)
+(define_insn "*combine_vcvtf2i"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (fix:SI (fix:SF (mult:SF (match_operand:SF 1 "s_register_operand" "t")
+ (match_operand 2
+ "const_double_vcvt_power_of_two" "Dp")))))]
+ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
+ "vcvt%?.s32.f32\\t%1, %1, %v2\;vmov%?\\t%0, %1"
+ [(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
+ (set_attr "ce_count" "2")
+ (set_attr "type" "f_cvtf2i")
+ (set_attr "length" "8")]
+ )
+
;; Store multiple insn used in function prologue.
(define_insn "*push_multi_vfp"
[(match_parallel 2 "multi_register_push"
diff --git a/gcc/testsuite/gcc.target/arm/fixed_float_conversion.c b/gcc/testsuite/gcc.target/arm/fixed_float_conversion.c
new file mode 100644
index 0000000..4b3a223
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/fixed_float_conversion.c
@@ -0,0 +1,17 @@
+/* Check that vcvt is used for fixed and float data conversions. */
+/* { dg-do compile } */
+/* { dg-options "-O1 -mfpu=vfp3" } */
+/* { dg-require-effective-target arm_vfp_ok } */
+
+float fixed_to_float (int i)
+{
+ return ((float)i / (1 << 16));
+}
+
+int float_to_fixed (float f)
+{
+ return ((int)(f * (1 << 16)));
+}
+
+/* { dg-final { scan-assembler "vcvt.f32.s32" } } */
+/* { dg-final { scan-assembler "vcvt.s32.f32" } } */
