Hi James,
Thanks for the review! I committed it on trunk.
Is it Okay to backport this patch to release branch 5, 6,7?
It applies cleanly without any logic changes.
Regards,
Renlin
On 31/01/18 17:56, James Greenhalgh wrote:
On Tue, Jan 30, 2018 at 03:45:17PM +0000, Renlin Li wrote:
Hi Richard,
Thanks for the review!
On 29/01/18 20:23, Richard Sandiford wrote:
The patch looks good to me FWIW. How about adding something like
the following testcase?
------------------------------------
/* { dg-do run } */
/* { dg-options "-O2" } */
typedef void (*fun) (void);
void __attribute__ ((noipa))
f (fun x1)
{
register fun x2 asm ("x16");
int arr[5000];
int *volatile ptr = arr;
asm ("mov %0, %1" : "=r" (x2) : "r" (x1));
x2 ();
}
void g (void) {}
int
main (void)
{
f (g);
}
------------------------------------
It was hard for me to construct an test case at that time.
Your example here exactly reflect the problem. The code-gen before the change
is:
f:
mov x16, 20016
sub sp, sp, x16
add x0, sp, 16
mov x16, 20016
str x0, [sp, 8]
add sp, sp, x16
br x16
After the change to the register constraint:
f:
mov x16, 20016
sub sp, sp, x16
// Start of user assembly
// 9 "indirect_tail_call_reg.c" 1
mov x16, x0
// 0 "" 2
// End of user assembly
add x0, sp, 16
str x0, [sp, 8]
mov x0, x16
mov x16, 20016
add sp, sp, x16
br x0
I updated the patch with the new test case,
the wording about the register constraint is also updated.
This patch is OK.
Thanks,
James
gcc/ChangeLog:
2018-01-30 Renlin Li <renlin...@arm.com>
* config/aarch64/aarch64.c (aarch64_class_max_nregs): Handle
TAILCALL_ADDR_REGS.
(aarch64_register_move_cost): Likewise.
* config/aarch64/aarch64.h (reg_class): Rename CALLER_SAVE_REGS to
TAILCALL_ADDR_REGS.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Rename CALLER_SAVE_REGS to
TAILCALL_ADDR_REGS. Remove IP registers.
* config/aarch64/aarch64.md (Ucs): Update register constraint.
gcc/testsuite/ChangeLog:
2018-01-30 Richard Sandiford <richard.sandif...@linaro.org>
* gcc.target/aarch64/indirect_tail_call_reg.c: New.
