Hi Roger,
The patch looks sane. Have you run dejagnu test suite?
Thanks,
Claudiu
-Original Message-
From: Roger Sayle
Sent: Friday, September 29, 2023 6:54 PM
To: gcc-patches@gcc.gnu.org
Cc: Claudiu Zissulescu
Subject: [ARC PATCH] Use rlc r0,0 to implement scc_ltu (i.e. carry_flag
1:02 AM
To: Roger Sayle ; Claudiu Zissulescu
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [ARC PATCH] Use rlc r0, 0 to implement scc_ltu (i.e. carry_flag ?
1 : 0)
On 9/29/23 15:11, Roger Sayle wrote:
>
> Hi Claudiu,
>> The patch looks sane. Have you run dejagnu test suite?
>
> I
Hi Roger,
Everything is good. Ok for mainline.
Thank you for your contribution,
Claudiu
-Original Message-
From: Claudiu Zissulescu
Sent: Sunday, October 1, 2023 5:33 PM
To: Jeff Law ; Roger Sayle
Cc: gcc-patches@gcc.gnu.org
Subject: RE: [ARC PATCH] Use rlc r0, 0 to implement scc_ltu
: gcc-patches@gcc.gnu.org
Cc: Claudiu Zissulescu
Subject: [ARC PATCH] Split SImode shifts pre-reload on !TARGET_BARREL_SHIFTER.
Hi Claudiu,
It was great meeting up with you and the Synopsys ARC team at the GNU tools
Cauldron in Cambridge.
This patch is the first in a series to improve SImod
Update description.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc-protos.h | 2 -
gcc/config/arc/arc.cc | 33 ++
gcc/config/arc/arc.h| 16 -
gcc/config/arc/arc.md | 125 ++--
gcc/config/arc/arc.opt | 4 +-
gc
.c: Set it to XFAIL.
Signed-off-by: Claudiu Zissulescu
---
gcc/testsuite/gcc.target/arc/add_n-combine.c | 2 +-
gcc/testsuite/gcc.target/arc/firq-4.c | 1 -
gcc/testsuite/gcc.target/arc/firq-6.c | 1 -
gcc/testsuite/gcc.target/arc/mtune-ARC600.c| 4
gcc/testsuite
/arc.md: Update patterns which uses '%&'.
gcc/testsuite/
* gcc.target/arc/loop-3.c: Update test.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.cc | 9 -
gcc/config/arc/arc.md | 18 +-
gcc/testsuite/gcc.targ
gcc/testsuite:
* gcc.target/arc/enter-dw2-1.c: Remove tests when using linux
build.
* gcc.target/arc/tls-ld.c: Update test.
* gcc.target/arc/tls-le.c: Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/testsuite/gcc.target/arc/enter-dw2-1.c | 18
.
(arc_output_libcall): Likewise.
* config/arc/arc.md: Remove ccfsm references and update related
instruction patterns.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc-passes.def | 6 -
gcc/config/arc/arc-protos.h | 7 -
gcc/config/arc/arc.cc | 830
ke pattern canonical.
(addsi_compare_2): Fix identation, constraint letters.
(addsi_compare_3): Likewise.
gcc/testsuite/
* gcc.target/arc/add_f-combine.c: New test.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.cc| 2 +-
g
Committed,
Claudiu
From: Andrew Burgess [andrew.burg...@embecosm.com]
Sent: Saturday, July 07, 2018 12:21 AM
To: Claudiu Zissulescu
Cc: gcc-patches@gcc.gnu.org; francois.bed...@synopsys.com; Claudiu Zissulescu
Subject: Re: [PATCH] [ARC] Add support for HS4x
From: claziss
gcc/
2017-06-14 Claudiu Zissulescu
* config/arc/arc.h (ADDITIONAL_REGISTER_NAMES): Add additional
register names.
---
gcc/config/arc/arc.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
Improve selection of short instruction for fp-moves.
gcc/
2018-05-17 Claudiu Zissulescu
* config/arc/arc.md (movsf_insn): Add short instruction selection.
* config/arc/constraints.md (CfZ): New constraint.
* config/arc/fpu.md (addssf3_fpu): Use CfZ constraint
gcc/
2018-05-09 Claudiu Zissulescu
* config/arc/arc.c (compact_memory_operand_p): Check for uncached
accesses as well.
(arc_is_uncached_mem_p): uncached applies to both the variable and
the pointer.
testsuite/
2018-05-09 Claudiu Zissulescu
Update the list of default optimizations used for size compilations.
gcc/
2018-07-10 Claudiu Zissulescu
* common/config/arc/arc-common.c (arc_option_optimization_table):
Update default optimizations for size.
---
gcc/common/config/arc/arc-common.c | 13 +
1 file
From: claziss
Use new align_lables struct instead of the deprecated align_labels_log
variable. Committed as obvious.
2018-07-17 Claudiu Zissulescu
* config/arc/arc.c (arc_label_align): Use align_labels instead of
deprecated align_labels_log.
git-svn-id: svn+ssh
Pushed. Thank you for your review,
Claudiu
From: Andrew Burgess [andrew.burg...@embecosm.com]
Sent: Wednesday, July 25, 2018 3:49 PM
To: Claudiu Zissulescu
Cc: gcc-patches@gcc.gnu.org; francois.bed...@synopsys.com; claziss
Subject: Re: [PATCH 1/4] [ARC] Add
The mpy_dest_reg_operand is just a wrapper for
register_operand. Remove it.
gcc/
* config/arc/arc.md (mulsi3_700): Update pattern.
(mulsi3_v2): Likewise.
* config/arc/predicates.md (mpy_dest_reg_operand): Remove it.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc
Hi Jeff,
> So I'm going to have to trust you on this one. It looks like you did
> more than just reorder the alternatives. For example, the constraints
> for operand0 look significantly different to me. THey're slightly
> different for operand1 as well (LR rather than Lc).
When we moved the AR
Ok, I'll push it asap.
Thank you for your help,
Claudiu
On Tue, Nov 5, 2019 at 8:19 PM Vineet Gupta wrote:
>
> Currently for hard float we need to check for
> __ARC_FPU_SP__ || __ARC_FPU_DP__ and for soft float inverse of that.
> So define single convenience macros for either cases
>
> gcc/
> x
Hi,
Fix ARC specific tests by improving the matching pattern and adding
the missing functionality in arc.exp
OK to appy?
Claudiu
gcc/tests
-xx-xx Claudiu Zissulescu
* gcc.target/arc/add_n-combine.c: Match add1/2/3 instruction in
output assembly.
* gcc.target
needs to
saved when ISR happens using a custom sequence.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc-protos.h (gen_mlo): Remove.
(gen_mhi): Likewise.
* config/arc/arc.c (AUX_MULHI): Define.
(arc_must_save_reister): Special handling for r
have the corresponding RF16 object attribute
set.
This patch qualifies the relevant hand-made assembly files to
RF16 config, and also adds generic c-functions for the one which are
not.
libgcc/
-xx-xx Claudiu Zissulescu
* config/arc/crti.S: Add RF16 object attribute.
* config
Like `packed` type attribute, the ARC's `uncached` type attribute
needs to be propagated to each member of the struct where it is used.
Fix this behavior and add a test.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.c (arc_is_uncached_mem_p): Check struct
attribut
The ARC's 600 multiplication instruction can accept signed 12 bit
instructions.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.c (arc_rtx_costs): Update mul64 cost.
---
gcc/config/arc/arc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/gcc/config/arc/arc.c
The ARC 600 MUL64 instructions are using mlo/mhi registers to pass the
64-bit result. However, the mlo/mhi registers are not swapping
depending on endianess. Update multiplication patterns to reflect
this fact.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.md (mulsidi_600
This option was used to control the short instruction selection. However,
there is no difference in cycles if we use or not a short instruction,
and always someone wants a smaller program.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.c (arc_conditional_register_usage): R0-R3
2 for any load/store instruction. The
latter one can be overwritten by using cost attribute for an
instruction. Due to this change, we need to update also a number of
instruction patterns with a new predicate to better reflect the costs.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc
For ARC, predicated instructions are not very friendly with size
optimizations, leading to increased object size. Disable if-conversion
step when optimized for size.
gcc/
-xx-xx Claudiu Zissulescu
* common/config/arc/arc-common.c (arc_option_optimization_table):
Disable if
Although the FDCMP (the double precision floating point compare instruction) is
added to the compiler, it is not properly used via cstoredi pattern. Fix it.
OK to apply?
Claudidu
-xx-xx Claudiu Zissulescu
* config/arc/arc.md (iterator SDF): Check TARGET_FP_DP_BASE
; To: gcc-patches@gcc.gnu.org
> Cc: Claudiu Zissulescu ;
> andrew.burg...@embecosm.com; linux-snps-...@lists.infradead.org;
> Vineet Gupta
> Subject: [PATCH] PR 92846: [ARC] generate signaling FDCMPF for hard float
> comparisons
>
> ARC gcc generates FDCMP instructions which raises
Hi Roger,
It looks good to me.
Thank you for your contribution,
Claudiu
-Original Message-
From: Roger Sayle
Sent: Tuesday, December 5, 2023 4:00 PM
To: gcc-patches@gcc.gnu.org
Cc: 'Claudiu Zissulescu'
Subject: [ARC PATCH] Add *extvsi_n_0 define_insn_and_split for PR 1107
HI Roger,
It looks good.
Thank you for your contribution,
Claudiu
-Original Message-
From: Roger Sayle
Sent: Sunday, December 24, 2023 1:38 AM
To: gcc-patches@gcc.gnu.org
Cc: 'Claudiu Zissulescu' ; 'Jeff Law'
Subject: [ARC PATCH] Table-driven ashlsi implementat
Hi Roger,
Looks good. Please proceed with your commit.
Thank you,
Claudiu
-Original Message-
From: Roger Sayle
Sent: Friday, November 3, 2023 9:43 PM
To: gcc-patches@gcc.gnu.org
Cc: 'Claudiu Zissulescu'
Subject: [ARC PATCH] Provide a TARGET_FOLD_BUILTIN target hook.
Looks good too. Please proceed with your commit.
Thank you for your contribution,
//Claudiu
-Original Message-
From: Roger Sayle
Sent: Monday, November 6, 2023 7:30 PM
To: gcc-patches@gcc.gnu.org
Cc: 'Claudiu Zissulescu'
Subject: [ARC PATCH] Improved DImode rotates and right
Sayle
Sent: Monday, November 6, 2023 8:37 PM
To: gcc-patches@gcc.gnu.org
Cc: 'Claudiu Zissulescu'
Subject: [ARC PATCH] Consistent use of whitespace in assembler templates.
This minor clean-up patch tweaks arc.md to use whitespace consistently in
output templates, always using a TAB b
Update my email address.
ChangeLog:
* MAINTAINERS: Update claziss email address.
Signed-off-by: Claudiu Zissulescu
---
MAINTAINERS | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 41319595bb5..ddeea7b497f 100644
--- a/MAINTAINERS
Thank u for the feedback. I hope this new patch solves the outstanding issues.
Please find it attached.
//Claudiu
0001-ARC-Add-basic-support-for-double-load-and-store-inst.patch
Description: 0001-ARC-Add-basic-support-for-double-load-and-store-inst.patch
Committed r232788
Thanks,
Claudiu
> -Original Message-
> From: Joern Wolfgang Rennecke [mailto:g...@amylaar.uk]
> Sent: Sunday, January 24, 2016 3:26 PM
> To: Claudiu Zissulescu; gcc-patches@gcc.gnu.org
> Cc: Francois Bedard; jeremy.benn...@embecosm.com
> Subject: Re:
Please find attached two small patches which are fixing two issues within the
ARC backend:
1. The first one fixes predicates used by arcset* patterns.
2. The second one rejects constant-constant comparisons. This situation may
happen durring CSE step.
Ok to apply?
Claudiu
Claudiu Zissulescu
gcc/
2016-01-25 Claudiu Zissulescu
* config/arc/arc.md (cstoresi4): Force operand into register.
(arcset): Fix predicate.
(arcsetltu): Likewise.
(arcsetgeu): Likewise.
(arcsethi): Likewise.
(arcsetls): Likewise.
---
gcc/config/arc/arc.md | 18
gcc/
2016-01-25 Claudiu Zissulescu
* config/arc/predicates.md (proper_comparison_operator): Reject
constant-constant comparison.
---
gcc/config/arc/predicates.md | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md
> FWIW, there's probably a missed optimization here - these constant -
> constant comparisons could be folded down further.
They are. The issue is when the CSE runs, wants to validate a new instruction
with the propagated constant, which will lead to errors as it checks the
proper_comaprison_o
into odd-even register pairs. This behavior
can be selected using -mabi option.
Feedback is welcomed,
Claudiu
gcc/
2016-02-01 Claudiu Zissulescu
* config/arc/arc-modes.def (CC_FPU, CC_FPUE, CC_FPU_UNEQ): New
modes.
* config/arc/arc-opts.h (FPU_SP, FPU_SF, FPU_SC, FPU_SD
From: claziss
Adding my self.
2016-02-02 Claudiu Zissulescu
* MAINTAINERS (Write After Approval): Add myself.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@233077
138bc75d-0d04-0410-961f-82ee72b054a4
---
ChangeLog | 4
MAINTAINERS | 1 +
2 files changed, 5 insertions
First, I will split this patch in two. The first part will deal with the FPU
instructions. The second patch, will try to address a new abi optimized for
odd-even registers as the comments for the mabi=optimized are numerous and I
need to carefully prepare for an answer.
The remaining of this ema
> P.S.: if code that is missing prototypes for stdarg functions is of no
> concern,
> there is another ABI alternative that might give good code density for
> architectures like ARC that have pre-decrement addressing modes and allow
> immediates to be pushed:
>
> You could put all unnamed argumen
Please find attached a reworked patch. It doesn't contain the ABI modifications
as I notified you earlier in an email. Also, you may have extra comments
regarding these original observations:
>+ /* ARCHS has 64-bit data-path which makes use of the even-odd paired
>+ registers. */
>+ if (
> > In the expand:
> > 18: cc:CC_FPU=cmp(r159:DF,r162:DF)
> > 19: r163:SI=cc:CC_FPU<0
> > 20: r161:QI=r163:SI#0
> > 21: r153:SI=zero_extend(r161:QI)
> > 22: cc:CC_ZN=cmp(r153:SI,0)
> > 23: pc={(cc:CC_ZN!=0)?L28:pc}
> >
> > Then after combine we get this:
> > 18: cc:CC_FP
> That sound like a bug. Have you looked more closely what's going on?
Right, I found it. Forgot to set the C_MODE for CC_FPU* modes in the
arc_mode_class[]. I will prepare a new patch with the proper handling.
Thanks!
Please find attached the amended patch for FPU instructions.
Ok to apply?
0001-ARC-Add-single-double-IEEE-precission-FPU-support.patch
Description: 0001-ARC-Add-single-double-IEEE-precission-FPU-support.patch
Thanks Joern,
Committed: r233451
> -Original Message-
> From: Joern Wolfgang Rennecke [mailto:g...@amylaar.uk]
> Sent: Saturday, February 13, 2016 12:42 AM
> To: Claudiu Zissulescu; gcc-patches@gcc.gnu.org
> Cc: francois.bed...@synopsys.com; jeremy.benn...@embecosm.co
This patch adds basic support for Synopsys' ARCv2 CPUs.
Can this be committed?
Thanks,
Claudiu
ChangeLog:
2015-08-27 Claudiu Zissulescu
* common/config/arc/arc-common.c (arc_handle_option): Handle ARCv2
options.
* config/arc/arc-opts.h: Add ARCv2
Just realized this patch haven't went thru to the mailing list. Reposted.
This patch adds basic support (libgcc) for Synopsys' ARCv2 CPUs.
Can this be committed?
Thanks,
Claudiu
ChangeLog:
2015-08-28 Claudiu Zissulescu
* config/arc/dp-hack.h: Add support
Hi,
Please find the updated patch. I will defer the secondary reload optimization
which will use the ld instructions with LIMM, for the time being.
Thank you,
Claudiu
gcc/ChangeLog:
2015-08-27 Claudiu Zissulescu
Hi,
Please find the updated patch. Both ARC patches were tested using dg.exp. The
ChangeLog entry is unchanged.
Thank you,
Claudiu
02-arcv2Updated.patch
Description: 02-arcv2Updated.patch
> If you can name a pre-existing testcase to trigger the assert, the patch is
> approved for separate check-in.
The patch solves the gcc.dg/pr29921-2.c error, visible for ARC700 architecture.
I will prepare a new patch for this error.
Thank you for the review,
Claudiu
This patch is committed (without the gen_compare_reg change).
Thanks Joern,
Claudiu
> Apart from the gen_compare_reg change, the patch is OK.
> If the v2 support mostly works like support for the other subtargets, you may
> check it in without the gen_compare_reg change.
> If that change is requ
This patch is committed.
Thanks Joern,
Claudiu
> -Original Message-
> From: Joern Wolfgang Rennecke [mailto:g...@amylaar.uk]
> Sent: Tuesday, November 10, 2015 3:02 PM
> To: Claudiu Zissulescu; gcc-patches@gcc.gnu.org
> Cc: Francois Bedard; jeremy.benn...@embecosm.co
Please find attached a patch that fixes the ARC backend ICE on pr29921-2 test
from gcc.dg (dg.exp).
The patch will allow generating conditional move also outside expand scope. The
error was triggered during if-conversion.
Ok to apply?
Claudiu
ChangeLog:
2015-11-11 Claudiu Zissulescu
Patch applied.
Thanks Joern,
Claudiu
> -Original Message-
> From: Joern Wolfgang Rennecke [mailto:g...@amylaar.uk]
> Sent: Wednesday, November 11, 2015 7:15 PM
> To: Claudiu Zissulescu; gcc-patches@gcc.gnu.org
> Cc: Francois Bedard
> Subject: Re: [PATCH][ARC] Fix
This patch adds support for atomic memory built-in for ARCHS and ARC700. Tested
with dg.exp.
OK to apply?
Thanks,
Claudiu
ChangeLogs:
gcc/
2015-11-12 Claudiu Zissulescu
* config/arc/arc-protos.h (arc_expand_atomic_op): Prototype.
(arc_split_compare_and_swap): Likewise
Properly emit DWARF2 related information while expanding epilogue. Remove
the -m[no]-epilogue-cfi option as it is not needed any longer. This patch
solves the dwarf2cfi errors observed while running dejagnu tests.
Ok to commit?
Claudiu
gcc/
2015-11-27 Claudiu Zissulescu
* config/arc
Ping. This patch is stalling for two weeks.
Thanks,
Claudiu
On Mon, Nov 16, 2015 at 11:18 AM, Claudiu Zissulescu
wrote:
> This patch adds support for atomic memory built-in for ARCHS and ARC700.
> Tested with dg.exp.
>
> OK to apply?
>
> Thanks,
> Claudiu
>
> Change
Hi Joern,
> > + insn = emit_insn (gen_blockage ());
>
> Is this actually part of the patch to fix cfi generation?
This instruction prevents the delay branch scheduler to speculatively use
epilogue instructions to fill up the delay slots. Hence, generating an assert
during dwarf2cfi execut
Hi,
> AFAICT, you use hardware synchronisation instruction for EMMODEL_SEQ,
> and compiler memory barriers for all other memory models (except
> MEMMODEL_RELAXED). That makes no sense; either the platform needs
> explicit instructions for memory coherency, or it doesn't.
Indeed, we on purpose mi
I will add this text before "*memory_barrier" pattern:
;; For ARCHS, we use a hardware data memory barrier that waits for
;; completion of current data memory operations before initiating
;; similar data memory operations.
Once done, I will commit it.
Thanks,
Claudiu
>
> Tested with dg.exp (wh
> The main point of having rtl epilogues is to allow such optimizations.
> Traditionally, we have said that at -O1, it is OK to curb optimizations for
> the
> sake of having programs that are saner to debug, while -O2 and above should
> just optimize, and the debug info generation is just thrown i
Patch applied: Committed r231509
Thanks,
Claudiu
> -Original Message-
> From: Joern Wolfgang Rennecke [mailto:g...@amylaar.uk]
> Sent: Wednesday, December 09, 2015 6:11 AM
> To: Claudiu Zissulescu; gcc-patches@gcc.gnu.org
> Cc: francois.bed...@synopsys.com; jeremy.benn.
>
> OTOH, the example you give also shows a much more nuanced approach to
> throttling optimization:
> the patch doesn't dead all epilogue scheduling, but specifically tests for the
> presence of a frame related insn at the point where it could cause trouble.
Actually, in my revised patch I do m
Early expand ADDDI3 and SUBDI3 for better code gen.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.md (adddi3): Early expand the 64bit operation into
32bit ops.
(subdi3): Likewise.
(adddi3_i): Remove pattern.
(subdi3_i): Likewise.
---
gcc/config
Add length attribute to eh_return pattern.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.md (eh_return): Add length info.
---
gcc/config/arc/arc.md | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index
raint. If so, a small data access is
generated. This patch fixes execute' pr93249 failure.
gcc/
xxxx-xx-xx Claudiu Zissulescu
* config/arc/arc.c (leigitimate_small_data_address_p): Check if an
address has an offset which fits the scalling constraint for a
With the refurbish of ARC600' accumulator support, the mlo_operand
doesn't reflect the proper low accumulator register for the newer
ARCv2 accumulator register used by the fma instructions, replace
it with accl_operand predicate.
gcc/
xxxx-xx-xx Claudiu Zissulescu
* config/
Thank you for your review. All 4 patches are pushed.
Claudiu
From: Jeff Law
Sent: Friday, February 28, 2020 11:15 PM
To: Claudiu Zissulescu ; gcc-patches@gcc.gnu.org
Cc: Claudiu Zissulescu ; Francois Bedard
; andrew.burg...@embecosm.com
Subject: Re: [PATCH 4
Add ARC entry for gcc-10/changes.html
---
htdocs/gcc-10/changes.html | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html
index 53d0ca08..4e27c05b 100644
--- a/htdocs/gcc-10/changes.html
+++ b/htdocs/gcc-10/chan
The mmixed-code option is obsolete, remove it.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.c (arc_override_options): Remove
TARGET_MIXED_CODE reference.
* config/arc/arc.md (abssi2_mixed): Remove pattern.
* config/arc/arc.h (TARGET_MIXED_CODE): Remove
The munalign-prob-threshold option is obsolete, remove it.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.opt (munalign-prob-threshold): Remove option.
* doc/invoke.texi (ARC): Remove munalign-prob-threshold doc.
* config/arc/arc.c (arc_unalign_branch_p): Remove
The malign-call option is obsolete, remove it.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.opt (malign-call): Remove option.
* doc/invoke.texi (ARC): Remove malign-call doc.
* common/config/arc/arc-common.c (arc_option_optimization_table):
Remove malign
Done 🙂 Thank you for your review,
Claudiu
From: Martin Sebor
Sent: Tuesday, March 3, 2020 6:47 PM
To: Claudiu Zissulescu ; gcc-patches@gcc.gnu.org
Cc: ger...@pfeifer.com ; l...@redhat.com ;
Francois Bedard ; Claudiu Zissulescu
; andrew.burg...@embecosm.com
I will rework the patches preserving the option. Shall I add a deprecate
message as well?
//Claudiu
From: Jeff Law
Sent: Tuesday, March 3, 2020 7:00 PM
To: Richard Biener ; Claudiu Zissulescu
Cc: GCC Patches ; Francois Bedard
; Claudiu Zissulescu ; Andrew
on 64 bit datum by the combiner, hence, the error. This
patch is stepping up the optimization level which will generate the
macu instruction at the expand time.
xxxx-xx-xx Claudiu Zissulescu
* gcc.target/arc/tumaddsidi4.c: Step-up optimization level.
Signed-off-by: Claudiu Zissulescu
It looks great 🙂 I'll keep in mind this tip next time.
Thank you,
Clauidu
From: Gerald Pfeifer
Sent: Saturday, March 7, 2020 11:05 PM
To: Claudiu Zissulescu ; Martin Sebor
Cc: gcc-patches@gcc.gnu.org ; Jeff Law
; Francois Bedard ; Claudiu Zissu
gcc9 branch as well.
OK to apply?
Claudiu
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.c (arc_legitimize_pic_address): Consider UNSPECs
as well, if interesting recover the symbol and re-legitimize the
pic address.
gcc/testsuite/
-xx-xx Claudiu Zissulescu
K to apply?
Claudiu
gcc/
xxxx-xx-xx Claudiu Zissulescu
Shahab Vahedi
* config/arc/arc.md (movsi_ne): Reorder instruction variants.
testsuite/
-xx-xx Shahab Vahedi
* gcc.target/arc/delay-slot-limm.c: New test.
---
gcc/config/arc/arc.md
Hi Andrew,
Please find a set of three patches for trunk as fallows:
[ARC] Cleanup sign/zero extend patterns
This is just insn patterns cleanup.
[ARC] Update mea option documentation
Update -mea option documentation.
[ARC] Don't split ior/mov predicated insns.
Found a
Cleanup sign/zero extend patterns (corrects the asm output string and
constraint letters).
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.md (zero_extendqihi2_i): Cleanup pattern.
(zero_extendqisi2_ac): Likewise.
(zero_extendhisi2_i): Likewise
Do not split immediate constants for predicated instructions.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.c (arc_split_ior): Add asserts.
(arc_split_mov_const): Likewise.
(arc_check_ior_const): Do not match known short immediate values.
* config/arc
Update -mea option documentation.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.opt (mea): Update help string.
* doc/invoke.texi(ARC): Update mea option info.
---
gcc/config/arc/arc.opt | 2 +-
gcc/doc/invoke.texi| 2 +-
2 files changed, 2 insertions(+), 2 deletions
ARC processors can use scaled addresses, i.e., the offset part of the
load address can be shifted by 2 (multiplied by 4). Add this pattern
and a test for it.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.md (load_scaledsi): New pattern.
testcase/
-xx-xx Claudiu Zissulescu
Use arc-passes.def to register ARC specific passes.
Ok to apply?
Claudiu
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc-protos.h (make_pass_arc_ifcvt): Declare.
(make_pass_arc_predicate_delay_insns): Likewise.
* config/arc/arc.c (class pass_arc_ifcvt): Reformat
The patterns neg_scc_insn and not_scc_insn are not correct, leading to
failing pr77309 test for ARC700. Add two new bic compare with zero
patterns to improve output code.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.md (bic_f): Use cc_set_register predicate
Thank you for your review, patch pushed.
//Claudiu
On Wed, Nov 20, 2019 at 1:58 AM Jeff Law wrote:
>
> On 11/19/19 2:02 AM, Claudiu Zissulescu wrote:
> > Use arc-passes.def to register ARC specific passes.
> >
> > Ok to apply?
> > Claudiu
> >
> &g
You are right, I should start with cleaning up the movsi pattern :) I
will come back to you with a proper patch when it is ready.
Thank you,
Claudiu
On Wed, Nov 20, 2019 at 2:00 AM Jeff Law wrote:
>
> On 11/19/19 2:02 AM, Claudiu Zissulescu wrote:
> > ARC processors can use scal
laudiu Zissulescu wrote:
> > The patterns neg_scc_insn and not_scc_insn are not correct, leading to
> > failing pr77309 test for ARC700. Add two new bic compare with zero
> > patterns to improve output code.
> >
> > gcc/
> > -xx-xx Claudiu Zissulescu
>
It seems it leads to this commit
c1760d8b599ddd7253b3a72f5219f0457f8d3130, but I need to double check.
Thank you Jeff,
Claudiu
On Thu, Nov 21, 2019 at 6:30 PM Jeff Law wrote:
>
> On 11/21/19 9:21 AM, Claudiu Zissulescu wrote:
> > Thank you for the feedback.
> >
> > Re
PING
On Mon, Nov 11, 2019 at 4:42 PM Claudiu Zissulescu wrote:
>
> Hi,
>
> Fix ARC specific tests by improving the matching pattern and adding
> the missing functionality in arc.exp
>
>
> OK to appy?
> Claudiu
>
>
> gcc/tests
> -xx-xx Claudiu Zissules
Thank you for your review. Pushed,
Claudiu
On Thu, Nov 21, 2019 at 9:13 PM Jeff Law wrote:
>
> On 11/21/19 9:35 AM, Claudiu Zissulescu wrote:
> > PING
> >
> > On Mon, Nov 11, 2019 at 4:42 PM Claudiu Zissulescu
> > wrote:
> >>
> >> Hi,
> >&
From: claziss
Hi Andrew,
Apologizes for the disconfort, please find the patch that works on the head.
Thanks,
Claudiu
gcc/
2016-12-13 Claudiu Zissulescu
Andrew Burgess
* config/arc/arc-protos.h (arc_compute_function_type): Change prototype
Just for the record, here it is the updated documentation as suggested. And,
indeed the description may very well be suited for NIOS io-variant as well.
Thank you Sandra,
Claudiu
---
gcc/doc/extend.texi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/gcc/doc/extend.texi b/gcc/d
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