> > OTOH, the example you give also shows a much more nuanced approach to > throttling optimization: > the patch doesn't dead all epilogue scheduling, but specifically tests for the > presence of a frame related insn at the point where it could cause trouble.
Actually, in my revised patch I do move the blockage instruction earlier on, before emitting any epilogue related instruction. > Or have some target hook to make it not even bother filling delay slots > speculatively; for targets that can fully unexpose the delay slot, like SH and > ARC >= ARC700, this aspect of fill_eager_delay_slots only mucks up > schedules and increases code size. > GCC has such a target: bool TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P (void) [Target Hook] This predicate controls the use of the eager delay slot filler to disallow speculatively executed instructions being placed in delay slots. Targets such as certain MIPS architectures possess both branches with and without delay slots. As the eager delay slot filler can decrease performance, disabling it is beneficial when ordinary branches are available. Use of delay slot branches filled using the basic filler is often still desirable as the delay slot can hide a pipeline bubble. We can enable this hook for ARC and see what are the numbers. Initially, I thought that we may lose more by enabling this hook. What do u say? //Claudiu
