Thanks Joern, Committed: r233451
> -----Original Message----- > From: Joern Wolfgang Rennecke [mailto:g...@amylaar.uk] > Sent: Saturday, February 13, 2016 12:42 AM > To: Claudiu Zissulescu; gcc-patches@gcc.gnu.org > Cc: francois.bed...@synopsys.com; jeremy.benn...@embecosm.com > Subject: Re: [PATCH] [ARC] Add single/double IEEE precission FPU support. > > > > On 10/02/16 13:31, Claudiu Zissulescu wrote: > > Please find attached the amended patch for FPU instructions. > > > > Ok to apply? > +(define_insn "*cmpdf_fpu" > > I'm wondering - could you compare with +zero using a literal (adding an > alternative)? > (No need to hold up the main patch, but you can consider it for a follow-up > patch) > > (define_insn "*cmpsf_fpu_uneq" > + [(set (reg:CC_FPU_UNEQ CC_REG) > + (compare:CC_FPU_UNEQ > + (match_operand:DF 0 "even_register_operand" "r") > > Typo: probably should be *cmpdf_fpu_uneq > > + case CC_FPUmode: > + return !((code == LTGT) || (code == UNEQ)); > ` > strictly speaking, this shouldn't accept unsigned comparisons, although I > can't > think of a scenario where these would be presented in this mode, and the > failure mode would just be an abort in get_arc_condition_code. > > Otherwise, this is OK.
