On Sat, Nov 15, 2014 at 6:08 AM, Jiong Wang
wrote:
> 2014-11-15 0:15 GMT+00:00 Andrew Pinski :
>> On Tue, Sep 30, 2014 at 8:00 AM, Jiong Wang wrote:
>>> On 27/09/14 22:20, Kugan wrote:
>>>>
>>>>
>>>> On 23/09/14 01:58, Jiong Wang wrote:
&g
On Sat, Nov 15, 2014 at 7:21 AM, Andrew Pinski wrote:
> On Sat, Nov 15, 2014 at 6:08 AM, Jiong Wang
> wrote:
>> 2014-11-15 0:15 GMT+00:00 Andrew Pinski :
>>> On Tue, Sep 30, 2014 at 8:00 AM, Jiong Wang wrote:
>>>> On 27/09/14 22:20, Kugan wrote:
>>>&g
Add a few testcases which I had floating around in a private tree.
Most of these testcases failed in our private tree at one point due to
local changes. Since it is always good to have more testcases, I
decided to commit them.
I tested all of them on x86_64 with no failures.
Thanks,
Andrew
Chan
mpiles glibc on aarch64.
I filed https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63906 to record this issue.
My analysis so far has found that it is rematerizing the new value of
sp where the old value of sp is needed after an alloca.
Thanks,
Andrew Pinski
>
> So I've committed the rem
On Mon, Nov 17, 2014 at 12:04 PM, Sebastian Pop wrote:
> Andrew Pinski wrote:
>> diff --git a/gcc/config/aarch64/thunderx.md b/gcc/config/aarch64/thunderx.md
>> new file mode 100644
>> index 000..30e4395
>> --- /dev/null
>> +++ b/gcc/config/aarc
On Mon, Nov 17, 2014 at 12:36 PM, Jeff Law wrote:
> On 11/17/14 02:26, Jiong Wang wrote:
>>
>> as Pinski reported at
>>
>>https://gcc.gnu.org/ml/gcc-patches/2014-11/msg01967.html
>>
>> the previosu LR free patch on AArch64 cause one gcc_assert in
>> lra-elimination.c
>>
>> one of the problem i
On Mon, Nov 17, 2014 at 4:15 PM, Vladimir Makarov wrote:
> The following patch fixes
>
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63906
>
> LRA rematerialization checks SP offsets at origin and rematerialization
> places when trying to rematerialize an insn. But the offsets are not valid
> if
ion for the xgene1 micro-architecture
> +
> +(define_automaton "xgene1")
> +
> +(define_cpu_unit "decode_out_0" "xgene1")
> +(define_cpu_unit "decode_out_1" "xgene1")
> +(define_cpu_unit "decode_out_2" "xgene1&qu
tested for
aarch64-elf with no regressions.
Thanks,
Andrew Pinski
ChangeLog:
ipa/63981
* ipa-polymorphic-call.c (possible_placement_new):
Use POINTER_SIZE instead of GET_MODE_BITSIZE (Pmode).
(ipa_polymorphic_call_context::restrict_to_inner_class): Likewise.
(extr_type_from_vtbl_ptr_store
On Wed, Nov 19, 2014 at 5:11 PM, H.J. Lu wrote:
> On Wed, Nov 19, 2014 at 4:54 PM, Andrew Pinski wrote:
>> Hi,
>> For ILP32 on AARCH64, we have ptr_mode != Pmode (we have ptr_mode
>> being SImode while Pmode is DImode and POINTER_SIZE is 32). This
>> breaks ipa-
On Wed, Nov 19, 2014 at 5:35 PM, H.J. Lu wrote:
> On Wed, Nov 19, 2014 at 5:23 PM, Andrew Pinski wrote:
>> On Wed, Nov 19, 2014 at 5:11 PM, H.J. Lu wrote:
>>> On Wed, Nov 19, 2014 at 4:54 PM, Andrew Pinski wrote:
>>>> Hi,
>>>> For ILP32 on AARCH64, w
On Wed, Nov 19, 2014 at 5:37 PM, H.J. Lu wrote:
> On Wed, Nov 19, 2014 at 5:36 PM, Andrew Pinski wrote:
>> On Wed, Nov 19, 2014 at 5:35 PM, H.J. Lu wrote:
>>> On Wed, Nov 19, 2014 at 5:23 PM, Andrew Pinski wrote:
>>>> On Wed, Nov 19, 2014 at 5:11 PM, H.J. Lu wro
On Wed, Nov 19, 2014 at 5:53 PM, H.J. Lu wrote:
> On Wed, Nov 19, 2014 at 5:39 PM, Andrew Pinski wrote:
>> On Wed, Nov 19, 2014 at 5:37 PM, H.J. Lu wrote:
>>> On Wed, Nov 19, 2014 at 5:36 PM, Andrew Pinski wrote:
>>>> On Wed, Nov 19, 2014 at 5:35 PM, H.J. Lu wro
ler \$f30
...
FAIL: gcc.target/mips/movdf-1.c -O1 scan-assembler-times ldc1 1
...
FAIL: gcc.target/mips/movdf-2.c -O1 scan-assembler mthc1
FAIL: gcc.target/mips/movdf-2.c -O1 scan-assembler mtc1
...
FAIL: gcc.target/mips/movdf-3.c -O1 scan-assembler-times mtc1 2
...
Thanks,
Andrew Pinski
>
> Matthew
obvious after a test of aarch64-elf.
Thanks,
Andrew Pinski
ChangeLog:
* gcc.target/aarch64/test_frame_1.c: Expect only two loads of x30 (in
the epilogue).
* gcc.target/aarch64/test_frame_6.c: Likewise.
* gcc.target/aarch64/test_frame_2.c: Expect only one pair load of x30
and x19 (in the epilogue
Hi,
This is just a rebase of
https://gcc.gnu.org/ml/gcc-patches/2014-11/msg01615.html as requested
by https://gcc.gnu.org/ml/gcc-patches/2014-11/msg01736.html. Nothing
has changed in it.
OK? Built and tested on aarch64-elf with no regressions.
Thanks,
Andrew Pinski
ChangeLog:
* config
Hi,
As discussed at
https://gcc.gnu.org/ml/gcc-patches/2014-10/msg00997.html, this is the
one line patch which improves shrink wrapping for lo_sum.
OK? Bootstrapped and tested on x86_64 and built and tested for
aarch64-elf with no regressions. It fixes shrink_wrap_symbol_ref_1.c
which was fail
aarch64 cross compile on an
older system where objcopy did not understand aarch64.
OK? Bootstrapped and tested on x86_64 with no regressions. Also
tested with a combined build for a cross compiler to
aarch64-linux-gnu.
Thanks,
Andrew Pinski
* Makefile.def (flags_to_pass): Pass
Hi,
On some simulators (Octeon simple-exec) argc can be greater than 2.
This causes initlist-lifetime1.C and initlist-lifetime2.C to fail.
To fix this, I use a volatile variable.
Committed as obvious after testing on x86_64.
Thanks,
Andrew Pinski
* g++.dg/cpp0x/initlist-lifetime1.C
Hi,
While looking at what patches I had in the internal tree here at
Cavium, I noticed two more testcases which I did upstream already.
One testcase for PR 53135 (reduced from dhcp-server) and another one
for an ICE which showed up while improving PHI-OPT (reduced from
gnupg-2.0.18).
Committed a
0..eeed665
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/pr64015.c
> @@ -0,0 +1,7 @@
> +/* { dg-do compile } */
> +/* { dg-options " -O2 " } */
> +int
> +test (unsigned short a, unsigned char b)
> +{
> + return a > 0xfff2 && b > 252;
> +}
Since this testcase is generic (except for the -O2), it really should
go into gcc.c-torture/compile instead of remove the two dg-*
directives so it can be tested on more than AARCH64 and on more
optimization levels.
Thanks,
Andrew Pinski
>
>
>
scalar version, I am proposing this patch
to make them consistent.
OK? Build and tested on aarch64-elf with no regressions.
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/aarch64-simd-builtins.def (bswap): Use CF2 rather
than CF10 so 2 is appended on the code.
* config
This patch is incorrect as get_imp is exported from libobjc.so. See
libobjc.def. I would rather use -std=gnu90 to compile these source
files as you are changing the exported symbols.
This also fixes bug 63863.
Thanks,
Andrew Pinski
>
>
> 2014-11-25 Uros Bizj
aarch64_float_const_representable_p in aarch64.c.
Thanks,
Andrew Pinski
ChangeLog:
* gcc.c-torture/execute/20141125-1.c: New testcase.
Index: testsuite/gcc.c-torture/execute/20141125-1.c
===
--- testsuite/gcc.c-torture/execute/20141125-1.c(revision 0
lds ();
> + return res;
> }
>
> /* Perform "late" intraprocedural SRA. */
> diff --git a/gcc/tree-ssa-sccvn.c b/gcc/tree-ssa-sccvn.c
> index 44656ea..cdb3850 100644
> --- a/gcc/tree-ssa-sccvn.c
> +++ b/gcc/tree-ssa-sccvn.c
> @@ -4410,29 +4410,6 @@ get_next_value_
bootstrapped and tested this on both aarch64-linux-gnu and
x86_64-linux-gnu with no regression on either.
Thanks,
Andrew Pinski
ChangeLog:
* lra.c (lra_substitute_pseudo): Use gen_lowpart_if_possible
instead of gen_rtx_SUBREG/gen_lowpart_SUBREG.
testsuite/ChangeLog
On Wed, Nov 26, 2014 at 2:00 PM, Andrew Pinski wrote:
> Hi,
> The problem here is lra_substitute_pseudo calls gen_rtx_SUBREG with
> a VOIDmode (const_int) argument but really it should not be calling
> gen_rtx_SUBREG directly instead it should be using
> gen_lowpart_if_possib
On Sat, Nov 29, 2014 at 5:15 PM, Segher Boessenkool
wrote:
> On Thu, Nov 27, 2014 at 05:44:30PM -0800, Segher Boessenkool wrote:
>> The first three of these are from the previous series, with hopefully
>> all comments addressed.
>>
>> The fourth simplifies the code that breaks up an arith insn wit
On Mon, Dec 1, 2014 at 10:26 AM, Jeff Law wrote:
> On 11/26/14 15:00, Andrew Pinski wrote:
>>
>> Hi,
>>The problem here is lra_substitute_pseudo calls gen_rtx_SUBREG with
>> a VOIDmode (const_int) argument but really it should not be calling
>> gen_rtx_SUB
On Tue, Feb 24, 2015 at 9:18 PM, Jeff Law wrote:
> On 02/17/15 08:31, Marcus Shawcroft wrote:
>>
>> On 9 February 2015 at 05:41, Andrew Pinski wrote:
>>>
>>> The problem here is that we get a symbol_ref which is SImode but for
>>> the sibcall patterns
On Tue, Mar 3, 2015 at 10:06 AM, Wilco Dijkstra wrote:
> This patch makes aarch64_min_divisions_for_recip_mul configurable for float
> and double. This allows
> CPUs with really fast or multiple dividers to return 3 (or even 4) if that
> happens to be faster
> overall. No code generation change
On Wed, Mar 4, 2015 at 12:00 AM, Marat Zakirov wrote:
> Hi all!
>
> Here is the patch which forces ASan to work on memory access without proper
> alignment. it's useful because some programs like linux kernel often cheat
> with alignment which may cause false negatives. This patch needs additional
On Tue, Mar 17, 2015 at 11:27 AM, Jeff Law wrote:
> On 03/17/2015 04:35 AM, Richard Biener wrote:
>
>>> I'll test both. In the common case, the cost is going to be the basic
>>> bookkeeping so that we can compute the transparent property. The
>>> actual
>>> computation of transparency and everyt
);
printf("second: %d.\n", b);
}
int f(int a, ...)
{
int b;
va_list ap;
va_start(ap, a);
g(a, ap);
va_end (ap);
return 0;
}
int main(void)
{
return f(2, FIRST, SECOND);
}
--- CUT ---
With the new glibc I get:
first: 4194304.
second: 1.
But with the old one I get :
first:
On Mon, Jun 15, 2015 at 2:09 AM, Martin Liška wrote:
> On 06/11/2015 08:19 PM, Richard Biener wrote:
>> On June 11, 2015 7:50:36 PM GMT+02:00, Jakub Jelinek
>> wrote:
>>> On Fri, Jun 12, 2015 at 12:58:12AM +0800, pins...@gmail.com wrote:
This is just a bug in the older compiler. There was a
On Tue, Jun 16, 2015 at 2:06 AM, Ramana Radhakrishnan
wrote:
>
>
> On 16/06/15 09:54, Eric Botcazou wrote:
>>
>> This is the C front-end + C family part.
>>
>> * doc/extend.texi (type attributes): Document
>> scalar_storage_order.
>> * doc/invoke.texi (Warnings): Document -Wno-scal
Hi,
This patch updates the schedule model to be more accurate and model
SIMD and fp instructions that I had missed out when I had the last
patch.
OK? Bootstrapped and tested on aarch64-linux-gnu with no regeessions.
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/thunderx.md
On Thu, Jun 25, 2015 at 3:57 PM, H.J. Lu wrote:
> On Thu, Jun 25, 2015 at 1:09 PM, H.J. Lu wrote:
>> On Tue, Jun 23, 2015 at 11:41 AM, Richard Sandiford
>> wrote:
>>> [A fair bit later than promised, sorry...]
>>>
>>> Mikhail posted a patch to make genflags generate the default HAVE_foo
>>> and
On Thu, Jun 25, 2015 at 1:24 AM, Ramana Radhakrishnan
wrote:
> Benedikt,
>
> On 25/06/15 08:01, pins...@gmail.com wrote:
>>
>>
>>
>>
>>
>>> On Jun 18, 2015, at 5:04 AM, Benedikt Huber
>>> wrote:
>>>
>>> arch64 offers the instructions frsqrte and frsqrts, for rsqrt estimation
>>> and
>>> a Newton-
/dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/rsqrt.c
> @@ -0,0 +1,113 @@
> +/* { dg-do run } */
> +/* { dg-options "-O3 -fno-inline --save-temps -ffast-math" } */
Maybe
On Mon, Jun 29, 2015 at 3:12 PM, Marc Glisse wrote:
> On Mon, 29 Jun 2015, Jeff Law wrote:
>
>>> That said - for this kind of patterns testcases that exercise the
>>> patterns
>>> on GIMPLE would be very appreciated.
>>
>> It may be the case that these patterns don't make a lot of sense on gimple
2d 100644
> --- a/gcc/config/aarch64/aarch64.c
> +++ b/gcc/config/aarch64/aarch64.c
> @@ -6716,6 +6716,11 @@ aarch64_parse_tune (void)
> }
>
>
> +/* Defined in config/aarch64/fma_steering.c. */
> +
> +void
> +aarch64_register_fma_steering (v
: unknown type name
>>>> 'ffi_go_closure'
>>>> makeFuncFFI(const struct __go_func_type *ftyp, ffi_go_closure *impl)
>>>> ^
>>>> make[4]: *** [reflect/makefunc_ffi_c.lo] Error 1
>>>
>>> What target?
>>
>> Why does it matter?
>
> Because I don't see that error here, obviously.
It fails for me with mips64-linux-gnu.
Thanks,
Andrew Pinski
>
>
> r~
>
On Sat, Jan 17, 2015 at 2:02 PM, Andreas Schwab wrote:
> Andrew Pinski writes:
>
>> On Sat, Jan 17, 2015 at 1:26 PM, Richard Henderson wrote:
>>> On 01/17/2015 11:07 AM, Andreas Schwab wrote:
>>>> Richard Henderson writes:
>>>>
>&
On Sun, Jan 18, 2015 at 11:58 AM, Christophe Lyon
wrote:
> On 16 January 2015 at 11:54, Marcus Shawcroft
> wrote:
>> On 15 January 2015 at 18:18, Richard Henderson wrote:
>>> On 12/15/2014 12:41 AM, Zhenqiang Chen wrote:
+(define_expand "cmp"
+ [(set (match_operand 0 "cc_register" "")
On Thu, Jan 15, 2015 at 8:18 AM, Mike Stump wrote:
> On Jan 14, 2015, at 3:50 AM, Tejas Belagod wrote:
>> As agreed here (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63971), please
>> can I reverse Andrew's patch
>> out(https://gcc.gnu.org/ml/gcc-patches/2014-11/msg02916.html)?
>
> Ok.
>
> Unl
ncorrect.
It is 39, 42 and 48 bits.
Thanks,
Andrew Pinski
>
> 2015-01-21 Jakub Jelinek
>
> PR sanitizer/64435
> * sanitizer_common/sanitizer_platform_limits_posix.h: Cherry pick
> upstream r226637.
> * sanitizer_common/sanitizer_p
;
> don't make me very confident in such a change.
> The extern prototypes really work with both -std=gnu89 and -std=gnu11 and
> thus will at least keep status quo.
Let's do that then.
This also fixes bug 63863.
Thanks,
Andrew Pinski
>
> Jakub
On Mon, Jan 26, 2015 at 1:55 AM, Hale Wang wrote:
> Hi,
>
> The GCC combine pass combines the insns even though they contain volatile
> registers. This doesn't make sence.
>
> The test case listed in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=46164
> shows the expected asm command "mov r1, r1" i
On Thu, Jan 29, 2015 at 6:58 PM, Mike Stump wrote:
> On Jan 29, 2015, at 4:15 PM, Joseph Myers wrote:
>> The patch is OK for GCC 6
>
> We will be releasing 5.x compilers for the next decade?! Does he really have
> to wait 10 years?
>
> Why not, just OK for stage 1?
You missed the memo on the v
use an ICE on any source code so I changed the
assert to be a sorry if either of the two arguments are not integer
constants.
OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions
and I was able to bootstrap without a modified libcpp.
Thanks,
Andrew Pinski
ChangeLog:
re.
An example:
+ "
+{
+ /* If this is a store, force the value into a register. */
+ if (MEM_P (operands[0]))
+operands[1] = force_reg (SFmode, operands[1]);
+ if (CONST_DOUBLE_P(operands[1]))
+operands[1] = force_const_mem(SFmode, operands[1]);
+}")
You do some of the ins
On Wed, Feb 4, 2015 at 8:46 AM, Matthew Fortune
wrote:
> Hi Catherine,
>
> I've made a first pass at writing up the MIPS changes for GCC 5.0.
> Could you take a read and see what needs some more work?
One comment below.
>
> Thanks,
> Matthew
>
> Index: htdocs/gcc-5/changes.html
> ==
e removal of _XOPEN_SOURCE is the right patch. I’ve
> not seen any substantive disagreement. I’d post and test that patch. A
> build person, a libobjc person, a reasonably an affected target person or a
> global person can approve in my book. I’m not any of them… If Pinski is
> happy with my approving it, he can weigh in. I’d be happy to approve it.
I am happy with which ever approach is decided as the safest and most portable.
Thanks,
Andrew Pinski
On Wed, Feb 4, 2015 at 10:32 AM, David Malcolm wrote:
> To build the jit docs, we need to use sphinx 1.0 or later; the
> 0.6.6 in EPEL 6 doesn't support all the directives we need.
>
> The alternate python-sphinx10 in EPEL 6 has 1.0.8:
> python-sphinx10-1.0.8-1.el6.noarch
> which is able to buil
On Thu, Feb 5, 2015 at 3:22 AM, Renlin Li wrote:
> Hi all,
>
> location information is missing when rewrite complex component-wise
> load/store.
>
> This patch add the location info to fix the recently gcc.dg/uninit-13.c and
> gcc.dg/uninit-17.c failures on arm target. The compiler warns uninitial
On Mon, Feb 2, 2015 at 11:37 PM, Jakub Jelinek wrote:
> On Mon, Feb 02, 2015 at 02:51:43PM -0800, Andrew Pinski wrote:
>> While trying to build the GCC 5 with GCC 5, I ran into an ICE when
>> building libcpp at -O0. The problem is the C++ front-end was not
>> folding sizeof
On Fri, Feb 6, 2015 at 5:02 PM, Andrew Pinski wrote:
> On Mon, Feb 2, 2015 at 11:37 PM, Jakub Jelinek wrote:
>> On Mon, Feb 02, 2015 at 02:51:43PM -0800, Andrew Pinski wrote:
>>> While trying to build the GCC 5 with GCC 5, I ran into an ICE when
>>> building libcpp at
?
> Regression tested on aarch64-elf.
Also bootstrapped and tested on aarch64-linux-gnu with no regressions
(and many testcases in libgomp passing now).
Thanks,
Andrew Pinski
>
> Thanks,
> Naveen
>
> 2015-02-02 Andrew Pinski
> Naveen H.
Like https://gcc.gnu.org/ml/gcc-patches/2015-01/msg02646.html, we
should xfail this testcase for aarch64 too.
OK? Bootstrapped and tested on aarch64-linux-gnu.
Thanks,
Andrew Pinski
ChangeLog:
* gcc.dg/tree-ssa/ssa-dom-cse-2.c: xfail for AARCH64 also.
commit
The aarch64 back-end has a dummy gty variable which is no longer
needed as there are other GTY marked variables now in aarch64.c This
should speed up (very slightly) PCH generate and reading in.
Committed as obvious after a build and test for aarch64-elf.
Thanks,
Andrew Pinski
ChangeLog
The problem here is that we get a symbol_ref which is SImode but for
the sibcall patterns we only match symbol_refs which use DImode. I
added a new testcase that tests the non-value sibcall pattern too.
OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions.
Thanks,
Andrew Pinski
load cif, fn, and
user_data by 32bit instead of 64bits as they are stored as pointers in
C code.
With this patch, I got no failures in the libffi testsuite that is
included with GCC.
OK? Built and tested on aarch64 with no regressions.
Thanks,
Andrew Pinski
ChangeLog:
* src/aarch64/ffitar
On Mon, Feb 9, 2015 at 3:20 PM, Pedro Alves wrote:
> Just like libiberty.h. So that C++ programs, such as GDB when built
> as a C++ program, can use it.
Why is not needed for GCC building with C++ compiler?
Thanks,
Andrew
>
> include/ChangeLog:
> 2015-02-09 Pedro Alves
>
> * floatfo
On Mon, Feb 9, 2015 at 5:51 PM, Thomas Preud'homme
wrote:
> Hi Eric,
>
> I'm taking over Zhenqiang's work on this. Comments and updated patch
> below.
>
>> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
>> ow...@gcc.gnu.org] On Behalf Of Eric Botcazou
>> > + rtx reg_equal = insn ? find_
On Tue, Feb 10, 2015 at 10:35 AM, Richard Henderson wrote:
> On 02/09/2015 12:40 AM, Andrew Pinski wrote:
>> #ifndef LIBFFI_ASM
>> +#ifdef __ILP32__
>> +typedef unsigned long long ffi_arg;
>> +typedef signed long long ffi_sarg;
>> +#else
>
> You need to s
On Tue, Feb 10, 2015 at 1:20 PM, Richard Henderson wrote:
> On 02/10/2015 11:02 AM, Andrew Pinski wrote:
>> +#define FFI_SIZEOF_JAVA_RAW 4
>
> Since aarch64 doesn't implement the raw java api, this is irrelevant.
Ok. This is what I applied to GCC after testing it (I don&
regressions and many libjava testcases now pass.
OK for boehm-gc upstream? I don't have write access to upstream
sources though, if approved there please apply it also.
Thanks,
Andrew Pinski
GCC ChangeLog:
* include/private/gcconfig.h (CPP_WORDSZ): Correct for AARCH64:ILP32.
(ALIG
_assert (mode == Pmode);
>> + emit_insn (gen_tlsie_small_sidi (tmp_reg, imm));
>> + }
>
>
> Andrew, do you recall the circumstance that trigger the mode == SImode
> code path through the above code? I've been trying to trigger this
> while working on
On Mon, Oct 27, 2014 at 3:23 PM, Steve Ellcey wrote:
>
> There are some MIPS patches that have been applied to the Google Android GCC
> tree but not been submitted to FSF GCC. I would like to get those patches
> checked in if possible. The first one is to add a new MIPS flag to turn
> off the u
On Mon, Oct 27, 2014 at 3:35 PM, Moore, Catherine
wrote:
>
>
>> -Original Message-----
>> From: Andrew Pinski [mailto:pins...@gmail.com]
>> Sent: Monday, October 27, 2014 6:32 PM
>> To: Steve Ellcey
>> Cc: Moore, Catherine; Matthew Fortune; GCC Patches
>
On Mon, Oct 27, 2014 at 3:44 PM, Moore, Catherine
wrote:
>
>
>> -Original Message-----
>> From: Andrew Pinski [mailto:pins...@gmail.com]
>> Sent: Monday, October 27, 2014 6:41 PM
>> To: Moore, Catherine
>> Cc: Steve Ellcey; Matthew Fortune; GCC Patches
>
ached one (though It is not updated for the new
cores including octeon3).
Thanks,
Andrew Pinski
>
> diff --git a/gcc/ifcvt.c b/gcc/ifcvt.c
> index 653653f..7bb2578 100644
> --- a/gcc/ifcvt.c
> +++ b/gcc/ifcvt.c
> @@ -1393,6 +1393,9 @@ noce_try_store_flag_mask (struct n
On Fri, Nov 7, 2014 at 7:08 AM, Richard Earnshaw wrote:
> On 21/10/14 22:37, Andrew Pinski wrote:
>> Hi,
>> To make aarch64.c a little smaller and a little easier to
>> understand, I have moved the rest of the cost tables
>> (cpu_addrcost_table, cpu_regmove_cost, cpu
I was getting a bootstrap failure but there was no
testsuite failures that was testing the problem.
Committed after a quick test to make sure the testcase is still a
valid executable testcase now.
Thanks,
Andrew Pinski
* gcc.c-torture/execute/20141107-1.c: New testcase.
Index: gcc.c-torture/ex
On Mon, Dec 2, 2013 at 2:51 PM, Jakub Jelinek wrote:
> Hi!
>
> On Sat, Nov 30, 2013 at 12:38:30PM +0100, Eric Botcazou wrote:
>> > Rather than adding do_pending_stack_adjust () in all the places, especially
>> > when it isn't clear whether emit_conditional_move will be called at all and
>> > wheth
simply convert
> a param or field type. Some examples:
>
> Functions passed a gsi
> ==
> Sometimes functions are passed a gsi, where it can be known that the gsi
> currently references a stmt of known kind (although that isn't
> necessarily obvious from
-gnu, ok?
>
> Ok. Can you please replace remaining HOST_WIDE_INT
> vestiges in there with [u]int64_t please?
This patch breaks the build on debian 6.0:
../../gcc/sreal.c: In member function ‘int64_t sreal::to_int() const’:
../../gcc/sreal.c:159: error: ‘INT64_MAX’ was not declared
On Tue, Nov 11, 2014 at 1:23 AM, Marc Glisse wrote:
> On Tue, 11 Nov 2014, Jakub Jelinek wrote:
>
>> On Tue, Nov 11, 2014 at 08:51:41AM +0100, Uros Bizjak wrote:
>>>
>>> Hello!
>>>
>> do $subject, and cleanup for always 64 bit hwi.
>>
>>
>> bootstrapped + regtested x86_64-unknown-l
I have found that if p was used below also. We still have if(p
!= 0). I just saw that recently when I was working on enhancing
PHI-opt.
Thanks,
Andrew Pinski
>
>> To achieve this the patch merges the mutually recursive functions
>> register_edge_assert_for_1() and register_edg
On Tue, Nov 11, 2014 at 4:54 AM, Richard Biener
wrote:
> On Tue, Nov 11, 2014 at 1:08 PM, Andrew Pinski wrote:
>> On Tue, Nov 11, 2014 at 1:23 AM, Marc Glisse wrote:
>>> On Tue, 11 Nov 2014, Jakub Jelinek wrote:
>>>
>>>> On Tue, Nov 11, 2014
aarch64-elf.
Thanks,
Andrew Pinski
ChangeLog:
Bug target/61997
* config.gcc (aarch64*-*-*): Set target_gtfiles to include
aarch64-builtins.c.
* config/aarch64/aarch64-builtins.c: Include gt-aarch64-builtins.h
at the end of the file.
Index: config.gcc
On Wed, Nov 12, 2014 at 2:54 AM, Jiong Wang wrote:
> On 12/11/14 10:01, Yangfei (Felix) wrote:
>
>> + if (GET_MODE (operands[0]) != DImode)
>> + FAIL;
>
>
> shouldn't SImode be considered for -mabi=ilp32 ?
I don't think it is needed for -mabi=ilp32 since word_mode is still
DImode for -
On Wed, Nov 12, 2014 at 9:25 PM, Teresa Johnson wrote:
> Added testcase. Here is the new patch:
>
> 2014-11-12
>
> gcc:
> PR tree-optimization/63841
> * tree.c (initializer_zerop): A constructor with no elements
> does not zero initialize.
Actually an empty constructor
On Wed, Nov 12, 2014 at 9:38 PM, Teresa Johnson wrote:
> On Wed, Nov 12, 2014 at 9:30 PM, Andrew Pinski wrote:
>> On Wed, Nov 12, 2014 at 9:25 PM, Teresa Johnson wrote:
>>> Added testcase. Here is the new patch:
>>>
>>> 2014-11-12
>>>
&g
aarch64_asan_shadow_offset is using the wrong
offset for ILP32. Change it to be a decent one.
OK? Bootstrapped and tested on aarch64-linux-gnu
with no regressions,
Thanks,
Andrew Pinski
ChangeLog:
* config/aarch64/aarch64.c (aarch64_asan_shadow_offset):
Fix ILP32 value.
---
gcc/config
On Fri, Nov 2, 2018 at 4:06 AM Richard Earnshaw (lists)
wrote:
>
> On 01/11/2018 01:52, Andrew Pinski wrote:
> > On Tue, Oct 30, 2018 at 10:21 AM Richard Earnshaw (lists)
> > wrote:
> >>
> >> On 30/10/2018 17:06, Andrew Pinski wrote:
> >>> Hi all,
gt;
> Bootstrap OK, OK for commit?
I think this should be in expand stage where there could be comparison
of the cost of the RTLs.
The only reason why it is faster for AARCH64 is the requirement of
moving between the GPRs and the SIMD registers.
Thanks,
Andrew Pinski
>
> ChangeLo
se we end up not merging the strs into an stp. It's questionable
> whether the use of STP is valid for volatile in the first place.
It is not valid as the architecture does not require stp to be atomic
so then the order of the stores can change
Thanks,
Andrew Pinski
> To avoid unnece
esent on POINTER_TYPEs.
>
> Here is an updated version that passed bootstrap/regtest on both
> x86_64-linux and i686-linux, ok for trunk?
Seems like this would fix PR91632 also.
Which has a C testcase included.
Thanks,
Andrew Pinski
>
> 2019-09-02 Jakub Jelinek
>
>
On Mon, Oct 29, 2018 at 12:29 AM Segher Boessenkool
wrote:
>
> This rewrites most of make_more_copies, in the process fixing a few PRs
> and some other bugs, and working around a few target problems. Certain
> notes turn out to actually change the meaning of the RTL, so we cannot
> drop them; and
tested on aarch64-linux-gnu with no regression.
Thanks,
Andrew Pinski
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def (octeontx): New.
(octeontx81): Likewise.
(octeontx83): Likewise.
* config/aarch64/aarch64-tune.md: Regenerate.
Index: gcc/config/aarch64/aarch64-cores.def
On Tue, Oct 30, 2018 at 10:21 AM Richard Earnshaw (lists)
wrote:
>
> On 30/10/2018 17:06, Andrew Pinski wrote:
> > Hi all,
> > There was a name change of the Products, ThunderX T81 and ThunderX
> > T83 to OcteonTX family name. This change was done a few years ago but
he testcases to cover
> the changed shift amount.
I think it might be better if we added new testcases instead of
modifying old ones in this case. The main reason is that if we test
an older compiler with the newer testsuite (which you can do), you
should get the tests failing.
The main
On Fri, Nov 9, 2018 at 10:09 AM Olivier Hainque wrote:
>
> Hello Wilco,
>
> Would you have further thoughts on the patches proposed in
>
> https://gcc.gnu.org/ml/gcc-patches/2018-10/msg01453.html
>
> ?
>
> There was:
>
> 1) * config/aarch64/aarch64.c (PROBE_STACK_FIRST_REG) : Redefine as
> R
LE_SIZE)
+{
+ error ("branch dilution: max branches (%d) must be \
+ less than granule size (%d)", MAX_BRANCH, GRANULE_SIZE);
+}
You should almost never use error in backend (there are a few
exceptions to that rule). Either use sorry or internal_error. Also
the way you wrapped
ide_int_to_tree (type, wi::bit_or (tem, tem2));
> + }
This seems incorrect for the case where BYTES_BIG_ENDIAN as far as I
can tell. With BYTES_BIG_ENDIAN, the bits position starts most
significiant rather than the least significiant. Sorry I am bring
this up after this has b
ene1,8A, AARCH64_FL_FOR_ARCH8
> | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, emag, 0x50, 0x000, 3)
I think you should add a comment to say why this order is required
like above for thunderxt88p1.
Thanks,
Andrew Pinski
> +
> /* APM ('P') cores. */
> AARCH64_CORE("x
bvious what word means here; it could be either 32bit or 64bit
depending on the option.
Also my other suggestion is create a new macro where you pass
riscv_align_data_type == riscv_align_data_type_word for the "(ALIGN) <
BITS_PER_WORD) " check to reduce the code duplication.
Thanks,
An
= x != 0;
>_3 = _1 & _2;
>_4 = (int) _3;
>D.2837 = (_Bool) _4;
>return D.2837;
> }
> `
>
> The reason for the inconsistency between these two behaviors is param
> logical-op-non-short-circuit. If we add the pattern to the match.pd
> file, we can only optimize the situation in which the statement is in
> the same basic block (logical-op-non-short-circuit=1, x86). But for
> a cross-basic block (logical-op-non-short-circuit=0, power), match.pd
> can't handle this situation.
>
> Another reason is that I found out maybe_fold_and_comparisons and
> maybe_fold_or_comparisons are not only called by ifcombine pass but
> also by reassoc pass. Using this method can basically unify param
> logical-op-non-short-circuit=0 or 1.
As mentioned before ifcombine pass should be using gimple-match
instead of fold_build. Try converting ifcombine over to gimple-match
infrastructure and add these to match.pd.
NOTE tree-ssa-phiopt should also be moved over to gimple-match but
that is a different issue.
Thanks,
Andrew Pinski
>
> Thanks,
> Lijia He
>
> >
> > jeff
> >
>
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