On Wed, Feb 4, 2015 at 8:46 AM, Matthew Fortune <matthew.fort...@imgtec.com> wrote: > Hi Catherine, > > I've made a first pass at writing up the MIPS changes for GCC 5.0. > Could you take a read and see what needs some more work?
One comment below. > > Thanks, > Matthew > > Index: htdocs/gcc-5/changes.html > =================================================================== > RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-5/changes.html,v > retrieving revision 1.77 > diff -r1.77 changes.html > 562a563,614 >> <h3 id="mips">MIPS</h3> >> <ul> >> <li>MIPS Releases 3 and 5 are now directly supported using >> <code>-mips32r3, >> -mips64r3, -mips32r5 and -mips64r5</code> instead of relying on the >> Release >> 2 options.</li> >> <li>Support for the Imagination P5600 processor has been added using >> <code>-march=p5600</code>. >> </li> >> <li>Support for the Cavium Networks Octeon3 processor has been added >> using >> <code>-march=octeon3</code>.</li> We are known as just Cavium now. That is remove the Networks part. Thanks, Andrew >> <li>MIPS Release 6 is now supported using <code>-mips32r6 and -mips64r6 >> </code>. >> <li>The previous o32 64-bit floating-point register support has been >> obsoleted and removed. This was previously enabled using <code>-mfp64 >> </code> which has been re-purposed for the new ABI extensions described >> below.</li> >> <li>New o32 ABI extensions have been added to enable software to >> transition >> away from the original layout of double-precision floating-point >> registers. >> <ul> >> <li>The first of these extensions is o32 FPXX which places restrictions >> on code-generation to never access the upper 32-bits of >> double-precision >> registers via odd-numbered single-precision registers. By default the >> odd-numbered single-precision registers are not used at all with this >> extension. o32 FPXX code is link compatible with all other o32 >> double-precision ABI variants and will execute correctly in all >> hardware >> FPU modes. Enable o32 FPXX using <code>-mabi=32 -mfpxx</code> for >> MIPS II onwards.</li> >> <li>The second extension is o32 FP64A which requires 64-bit >> floating-point registers and places a mandatory restriction on the use >> of >> odd-numbered single-precision registers. o32 FP64A is link compatible >> with all other o32 double-precision ABI variants. Enable o32 FP64A >> using <code>-mabi=32 -mfp64 -mno-odd-spreg</code> for MIPS32R2 onwards. >> </li> >> <li>Finally, the o32 FP64 extension which also requires 64-bit >> floating-point registers but permits the use of all single-precision >> registers. Enable o32 FP64 using <code>-mfp64</code> for MIPS32R2 >> onwards.</li> >> </ul> >> All new ABI variants can be enabled by default using configure time >> options <code>--with-fp-32=[32|xx|64]</code> and >> <code>--with(out)-odd-sp-reg-32</code>. It is strongly recommended that >> all vendors begin to set o32 FPXX as default ABI to be able to run the >> generated code on MIPSR5 cores alongside future MIPS SIMD (MSA) code and >> MIPSR6 cores.</li> >> <li>When using binutils 2.25 GCC will now pass options like >> <code>-msoft-float</code> and <code>-msingle-float</code> to the >> assembler. >> This change can affect inline assembly code that is built as soft-float >> but >> contains hard-float instructions. In such cases the code must be amended >> to use appropriate <code>.set</code> directives to override the global >> assembler options.</li> >> </ul> >>
