On Sun, Sep 1, 2024 at 5:20 PM Filip Kastl wrote:
>
> (I'm Cc-ing Diego since he originally contributed the VRP pass and Jeff
> because
> I've seen him in git blame on many lines of vr-values.cc around the place I
> would like to make modifications)
>
> Hello,
>
> In this RFC I'd like to propose
On Fri, Aug 30, 2024 at 7:05 PM Tobias Burnus wrote:
>
> Noticed that -save-tmp is ignored for parallel LTO. With this patch, the
> result is now:
>
> make -f ./a.ltrans.mk -j2 all
> [Leaving LTRANS ./a.ltrans.mk]
>
> instead of
>
> make -f /tmp/ccXgtcjJ.mk -j2 all
> [Leaving LTRANS /tmp/ccXgtcjJ.
On Fri, Aug 30, 2024 at 8:17 PM Tobias Burnus wrote:
>
> With HAVE_WORKING_FORK unset, I get an unused by set compile error.
>
> That's fixed with the attached patch.
OK
> Tobias
>
> PS: And if someone wonders what I am doing, see https://gcc.gnu.org/PR116535
On Sun, 1 Sep 2024, Prathamesh Kulkarni wrote:
> Hi,
> For the following test:
> #include
>
> int main()
> {
> svint32_t x;
> #pragma omp target map(x)
> x;
> return 0;
> }
>
> compiling with -fopenmp -foffload=nvptx-none results in following ICE:
>
> t_sve.c: In function 'main':
> t
On Mon, Sep 02, 2024 at 09:03:46AM +0200, Richard Biener wrote:
> > I have originally thought about solving this problem in the switch
> > conversion
> > pass. However, I think that would require basically detecting that the
> > "take
> > away the default case" transformation happened and then r
Hi!
The initial CLZ gimple-range-op.cc implementation handled just the
case where second argument to .CLZ is equal to prec, but in
r15-1014 I've added also handling of the -1 case. As the following
testcase shows, incorrectly though for the case where the first argument
has [0,0] range. If the s
On Mon, 2 Sep 2024, Jakub Jelinek wrote:
> Hi!
>
> The initial CLZ gimple-range-op.cc implementation handled just the
> case where second argument to .CLZ is equal to prec, but in
> r15-1014 I've added also handling of the -1 case. As the following
> testcase shows, incorrectly though for the ca
From: Piotr Trojanek
Routine Insert_Valid_Check only applies checks when Expr_Known_Valid
query returns False; there is no need to call this query before
inserting checks.
Code cleanup; behavior is unaffected.
gcc/ada/
* exp_imgv.adb (Expand_User_Defined_Enumeration_Image)
(Exp
From: Piotr Trojanek
Replace repeated calls to Sloc with uses of local constant Loc.
Code cleanup; behavior is unaffected.
gcc/ada/
* exp_ch3.adb (Expand_N_Object_Declaration): Replace calls to Sloc
with uses of Loc; turn variable Prag into constant.
Tested on x86_64-pc-linux-
From: Ronan Desplanques
Before this patch, the documentation of -gnaty0 used 0-based indexing
for column numbers while 1-based indexing is used everywhere else. This
patch makes this documentation use 1-based indexing, and also adds a
missing parenthesis.
gcc/ada/
* doc/gnat_ugn/buildin
From: Viljar Indus
gcc/ada/
* doc/gnat_ugn/building_executable_programs_with_gnat.rst: update
documentation for the -gnatw_l switch.
* usage.adb: Add -gnatw_l entry.
* gnat_ugn.texi: Regenerate.
Tested on x86_64-pc-linux-gnu, committed on master.
---
.../gnat_u
From: Eric Botcazou
The problem is that the size clause changes the floating-point format used
for the type, but it must not when this format is the widest format that is
supported in hardware on the target. Instead a padding type must be built
and the associated warning given.
gcc/ada/
When changing the scope for entities found in the entry body that is
mutated into a procedure, the compiler needs to look deeper than only
the top level entities as expansion may produce object declarations
which scopes are also the entry. For example, the tree after expansion
may look like:
pro
From: Ronan Desplanques
Before this patch, the gnat command sent to standard error pieces of
information that are a better match for standard output. This patch
makes this information go to standard output.
gcc/ada/
* gnatcmd.adb (GNATCmd): Fix standard output stream.
Tested on x86_64-
From: Bob Duff
...plus minor improvements to existing documentation.
gcc/ada/
* doc/gnat_rm/gnat_language_extensions.rst: I assume "extended set
of extensions" was a typo for "experimental set of extensions",
because "extended extensions" is repetitive and redundant. "in
From: Patrick Bernardi
Size of pthread data types now need to be defined for FreeBSD ports.
Traceback support for AArch64 FreeBSD is now defined.
gcc/ada/
* s-oscons-tmplt.c: Define sizes of pthread data types on FreeBSD.
* tracebak.c: Use GCC unwinder and adjust PC appropriatel
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ok for trunk?
This patch introduces new mode iterators and expands for the i386 architecture
to support partial vectorization of bf16 operations using AVX10.2 instructions.
These operations include addition, subtraction, multiplication, d
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ok for trunk?
This patch supports sminmax for partial vectorized V2BF/V4BF.
gcc/ChangeLog:
* config/i386/mmx.md (3): New define_expand for
V2BF/V4BFsmaxmin
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx10_2-partial-bf-v
PR libstdc++/116513
* libsupc++/compare (_S_fp_bits) [__fmt == _M68k_80bit]: Shift
padding out of exponent word.
---
libstdc++-v3/libsupc++/compare | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/libstdc++-v3/libsupc++/compare b/libstdc++-v3/libsup
Currently vect_get_vector_types_for_stmt only special-cases
IFN_MASK_STORE but there are now very many variants and simply
passing analysis without setting *VECTYPE will ICE duing SLP
discovery (noticed with IFN_SCATTER_STORE). The following
properly uses internal_store_fn_p. I also noticed we're
On Mon, 2 Sept 2024 at 10:02, Andreas Schwab wrote:
>
> PR libstdc++/116513
> * libsupc++/compare (_S_fp_bits) [__fmt == _M68k_80bit]: Shift
> padding out of exponent word.
OK for trunk.
The code is present since GCC 12.1 so it's your call as target
maintainer which branch
On Sat, 31 Aug 2024 at 05:51, Alexandre Oliva wrote:
>
>
> 30_threads/future/members/poll.cc has calibration code that, on
> systems with very low clock resolution, may spuriously fail to run.
> Even when it does run, low resolution and reasonable
> timeouts limit severely the viability of increas
On Thu, 1 Aug 2024 at 11:44, Alexandre Oliva wrote:
>
> When we get to test_pr91486_wait_until(), we're about 10s past the
> float_steady_clock epoch. This is enough for the 1s delta for the
> timeout to come out slightly lower when the futex-less wait_until
> converts the deadline from float_ste
From: Pan Li
This patch would like to allow the IMM operand of the unsigned
scalar .SAT_ADD. Like the operand 0, the operand 1 of .SAT_ADD
will be zero extended to Xmode before underlying code generation.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
gcc
Ping for https://gcc.gnu.org/pipermail/gcc-patches/2024-August/659796.html
For clarity's sake, here's the full patch with the adjustment I
mentioned earlier:
-- >8 --
This patch goes through all .cc files in gcc/cp and adds in any
auto_diagnostic_groups that seem to be missing by looking for any
The attached patch tries to fix the issue exposed by the PR:
The main ingredient is partitioning of the LTO work, e.g. by using
-flto-partition=max.
With -flto=2 (or higher or when a jobserver has been detected), not only
the LTO part is run in parallel but also the creation of the ltrans
fi
Ping.
On Wed, Aug 21, 2024 at 09:38:44AM +1000, Nathaniel Shead wrote:
> Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk?
>
> -- >8 --
>
> The Itanium ABI has specific rules for when virtual tables for dynamic
> classes should be emitted. However we didn't consider structures wi
Ping.
On Wed, Aug 21, 2024 at 09:40:25AM +1000, Nathaniel Shead wrote:
> Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk?
>
> -- >8 --
>
> The ICE in the linked PR is caused because maybe_clone_decl is not
> prepared to be called on a declaration that has already had clones
> cre
Ping.
On Wed, Aug 21, 2024 at 09:41:31AM +1000, Nathaniel Shead wrote:
> Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk?
>
> -- >8 --
>
> When compiling with '-fdeclone-ctor-dtor' (enabled by default with -Os),
> we run into issues where we don't correctly emit the underlying
>
Ping.
On Fri, Aug 23, 2024 at 10:02:44AM +1000, Nathaniel Shead wrote:
> On Thu, Aug 22, 2024 at 02:20:14PM -0400, Patrick Palka wrote:
> > On Mon, 12 Aug 2024, Nathaniel Shead wrote:
> >
> > > Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk?
> > >
> > > I tried to implement a re
On Mon, 2 Sep 2024, Tobias Burnus wrote:
> The attached patch tries to fix the issue exposed by the PR:
>
> The main ingredient is partitioning of the LTO work, e.g. by using
> -flto-partition=max.
>
> With -flto=2 (or higher or when a jobserver has been detected), not only the
> LTO part is run
> On 30 Aug 2024, at 14:05, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> Jennifer Schmitz writes:
>> This patch implements constant folding of binary operations for SVE
>> intrinsics
>> by calling the constant-folding mechanism of the middle-end
> On 30 Aug 2024, at 14:17, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> Jennifer Schmitz writes:
>> This patch implements constant folding for svdiv. If the predicate is
>> ptrue or predication is _x, it uses vector_const_binop with
>> aarch64_
> On 30 Aug 2024, at 14:21, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> Jennifer Schmitz writes:
>> This patch implements constant folding for svmul. If the predicate is
>> ptrue or predication is _x, it uses vector_const_binop with
>> aarch64_c
Jennifer Schmitz writes:
> @@ -1365,6 +1368,91 @@ simplify_const_binop (tree_code code, tree op, tree
> other_op,
>return NULL_TREE;
> }
>
> +/* Combine two (vector) constants ARG1 and ARG2 element-wise under operation
> + CODE using function ELT_CONST_BINOP to produce a new (vector) con
Jennifer Schmitz writes:
> diff --git a/gcc/config/aarch64/aarch64-sve-builtins.cc
> b/gcc/config/aarch64/aarch64-sve-builtins.cc
> index 5ca9ec32b69..60350e08372 100644
> --- a/gcc/config/aarch64/aarch64-sve-builtins.cc
> +++ b/gcc/config/aarch64/aarch64-sve-builtins.cc
> @@ -1132,6 +1132,30 @@
Jennifer Schmitz writes:
>> Does:
>>
>> svmul_n_u32_x (pg, svindex_u32 (4, 1), 2);
>>
>> get optimised to a single INDEX of #8, #2? It would be good to test
>> things like that if so.
>>
>> Looks good to me otherwise.
>>
>> Thanks,
>> Richard
> I tested this test case, but - unlike svdup - s
The main focus of this work is resolving issues in the aarch64-w64-mingw32
target related to enabling optimization with -O2, -O3, and LTO, fixing
relocations, and adding debugging information.
This patch series is supported by the binutils patch series.
https://sourceware.org/pipermail/binutils/20
The patch adds support for weak references. The original MinGW
implementation targets ix86, which handles weak symbols differently
compared to AArch64. In AArch64, the weak symbols are replaced by
other symbols which reference the original weak symbols, and the
compiler does not track the original
This patch enables DWARF and allows compilation with debugging
information by using "gcc -g". The unwind info is disabled for
the moment and will be revisited after SEH implementation for
the target.
gcc/ChangeLog:
* config/aarch64/aarch64.cc (TARGET_ASM_UNALIGNED_HI_OP):
Enable D
The patch resolves compilation issues for the C++ language. Previous
patch series contributed to C++ as well, however, C++ could not be
tested until we got a C++ compiler and could build at least a "Hello
World" C++ program, and in reality, more than that.
gcc/ChangeLog:
* config.gcc: Add
Symbols using GOT are not supported by the aarch64-w64-mingw32
target and should be excluded from the code models.
gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_symbol_binds_local_p):
Disable GOT for PECOFF target.
---
gcc/config/aarch64/aarch64.cc | 3 +++
1 file changed,
On Linux/x86_64,
6d294fb8ac9baf2624446deaa4c995b7a7719823 is the first bad commit
commit 6d294fb8ac9baf2624446deaa4c995b7a7719823
Author: Levy Hsu
Date: Mon Sep 2 10:24:46 2024 +0800
i386: Support vectorized BF16 FMA with AVX10.2 instructions
caused
FAIL: gcc.target/i386/avx10_2-bf-vecto
On Linux/x86_64,
b1f9fbb6da1a3ced57c3668cecc9f9449e1b237e is the first bad commit
commit b1f9fbb6da1a3ced57c3668cecc9f9449e1b237e
Author: Haochen Jiang
Date: Mon Sep 2 10:24:29 2024 +0800
i386: Auto vectorize sdot_prod, usdot_prod, udot_prod with AVX10.2
instructions
caused
FAIL: gcc.ta
On Linux/x86_64,
3b1decef83003db9cf8667977c293435c0f3d024 is the first bad commit
commit 3b1decef83003db9cf8667977c293435c0f3d024
Author: Hu, Lin1
Date: Mon Sep 2 10:24:36 2024 +0800
i386: Optimize generate insn for AVX10.2 compare
caused
FAIL: gcc.target/i386/avx10_2-compare-1b.c (test
LOCAL_LABEL_PREFIX has been changed to help the assembly
compiler recognize local labels. Emitting locals has been
replaced with the .lcomm directive to declare uninitialized
data without defining an exact section. Functions and objects
were missing declarations. Binutils was not able to distinguis
On Linux/x86_64,
f77435aa3911c437cba71991509eee57b333b3ce is the first bad commit
commit f77435aa3911c437cba71991509eee57b333b3ce
Author: Levy Hsu
Date: Mon Sep 2 10:24:49 2024 +0800
i386: Support vec_cmp for V8BF/V16BF/V32BF in AVX10.2
caused
FAIL: gcc.target/i386/avx10_2-bf-vector-cmpp
On Linux/x86_64,
29ef601973d7b79338694e59581d4c24bcd07f69 is the first bad commit
commit 29ef601973d7b79338694e59581d4c24bcd07f69
Author: Levy Hsu
Date: Mon Sep 2 10:24:47 2024 +0800
i386: Support vectorized BF16 smaxmin with AVX10.2 instructions
caused
FAIL: gcc.target/i386/avx10_2-bf-v
On Linux/x86_64,
f82fa0da4d9e1fdaf5e4edd70364d5781534ce11 is the first bad commit
commit f82fa0da4d9e1fdaf5e4edd70364d5781534ce11
Author: Levy Hsu
Date: Mon Sep 2 10:24:45 2024 +0800
i386: Support vectorized BF16 add/sub/mul/div with AVX10.2 instructions
caused
FAIL: gcc.target/i386/avx1
aarch64.cc has been updated to prevent emitting "symbol + offset"
for SYMBOL_SMALL_ABSOLUTE for the PECOFF target. "symbol + offset"
cannot be used in relocations for aarch64-w64-mingw32 due to
relocation requirements.
Instead, it will adjust the address by an offset with the
"add" instruction.
gc
The anchors have been disabled as they use symbol + offset, which is
not applicable for COFF AArch64.
gcc/ChangeLog:
* config/aarch64/aarch64.cc (TARGET_MIN_ANCHOR_OFFSET):
Keep default TARGET_MAX_ANCHOR_OFFSET for PECOFF target.
(TARGET_MAX_ANCHOR_OFFSET): Likewise.
---
The patch reuses the configuration for LTO from ix86 and adds the
aarch64 architecture to the list of supported COFF headers.
gcc/ChangeLog:
* config/aarch64/cygming.h (TARGET_ASM_LTO_START): New.
(TARGET_ASM_LTO_END): Likewise.
* config/i386/cygming.h (TARGET_ASM_LTO_STAR
In some cases, the alignment can be bigger than BIGGEST_ALIGNMENT.
The patch handles these cases.
gcc/ChangeLog:
* config/aarch64/aarch64-coff.h (ASM_OUTPUT_ALIGNED_LOCAL):
Change alignment.
---
gcc/config/aarch64/aarch64-coff.h | 10 ++
1 file changed, 10 insertions(+)
Hi Evgeny,
> On 2 Sep 2024, at 15:03, Evgeny Karpov wrote:
>
> External email: Use caution opening links or attachments
>
>
> The patch resolves compilation issues for the C++ language. Previous
> patch series contributed to C++ as well, however, C++ could not be
> tested until we got a C++ co
The following makes sure we handle a SLP load/store group from
a structure with complex and scalar members. This for example
happens in gcc.target/i386/pr106010-9a.c.
Bootstrap and regtest running on x86_64-unknown-linux-gnu.
* tree-vect-slp.cc (vect_build_slp_tree_1): Handle mixing
On Mon, 2 Sept 2024, 14:15 Kyrylo Tkachov, wrote:
> Hi Evgeny,
>
> > On 2 Sep 2024, at 15:03, Evgeny Karpov
> wrote:
> >
> > External email: Use caution opening links or attachments
> >
> >
> > The patch resolves compilation issues for the C++ language. Previous
> > patch series contributed to C
On Mon, 2 Sept 2024, 14:15 Kyrylo Tkachov, wrote:
> Hi Evgeny,
>
> > On 2 Sep 2024, at 15:03, Evgeny Karpov
> wrote:
> >
> > External email: Use caution opening links or attachments
> >
> >
> > The patch resolves compilation issues for the C++ language. Previous
> > patch series contributed to C
The patch adds a new instruction pattern to handle conditional branches with
equality checks between shifted arithmetic operands. This pattern optimizes the
use of shifted constants (with trailing zeros), making it more efficient.
For the C code:
void f5(long long a) {
if ((a & 0x212) == 0
The only GCN3 ISA device was remove (Fiji, gfx803) so all the GCN3-specific
code and features can be removed from the back-end.
gcc/ChangeLog:
* config/gcn/gcn-opts.h (enum gcn_isa): Delete ISA_GCN3.
(TARGET_GCN3): Delete.
(TARGET_GCN3_PLUS): Delete.
(TARGET_M0_LDS
Now that GCN3 support is gone, TARGET_GCN5_PLUS always evaluates to true, so
we can make that code unconditional, and remove all the "else" cases.
The ISA features TARGET_GLOBAL_ADDRSPACE, TARGET_FLAT_OFFSETS,
TARGET_EXPLICIT_CARRY, and TARGET_MULTIPLY_IMMEDIATE, are similarly also
redundant and c
The gfx803 "Fiji" device was deprecated in GCC 14, removed from LLVM 18, and
hasn't worked properly with the drivers since about ROCm 4.
This patch removes the device from GCC options and documentation, and removes
the direct mentions from the internals.
The TARGET_GCN3 support in the back-end is
On Fri, Aug 16, 2024 at 05:14:42PM +, Joseph Myers wrote:
> On Fri, 16 Aug 2024, Jakub Jelinek wrote:
>
> > Ok. So for now, should I work on a patch variant which tries to follow
> > what is in C23 right now?
>
> Not sure how useful having such a patch variant would be until we have a
> bet
Evgeny Karpov writes:
> Symbols using GOT are not supported by the aarch64-w64-mingw32
> target and should be excluded from the code models.
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64.cc (aarch64_symbol_binds_local_p):
> Disable GOT for PECOFF target.
I think we should instead pa
Evgeny Karpov writes:
> LOCAL_LABEL_PREFIX has been changed to help the assembly
> compiler recognize local labels. Emitting locals has been
> replaced with the .lcomm directive to declare uninitialized
> data without defining an exact section. Functions and objects
> were missing declarations. Bi
Evgeny Karpov writes:
> aarch64.cc has been updated to prevent emitting "symbol + offset"
> for SYMBOL_SMALL_ABSOLUTE for the PECOFF target. "symbol + offset"
> cannot be used in relocations for aarch64-w64-mingw32 due to
> relocation requirements.
> Instead, it will adjust the address by an offse
Evgeny Karpov writes:
> In some cases, the alignment can be bigger than BIGGEST_ALIGNMENT.
> The patch handles these cases.
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-coff.h (ASM_OUTPUT_ALIGNED_LOCAL):
> Change alignment.
Can you go into more detail? What kind of testcase requir
Evgeny Karpov writes:
> The main focus of this work is resolving issues in the aarch64-w64-mingw32
> target related to enabling optimization with -O2, -O3, and LTO, fixing
> relocations, and adding debugging information.
>
> This patch series is supported by the binutils patch series.
> https://so
Andi Kleen writes:
Ping^3
> Andi Kleen writes:
>
> PING^2 for the patch.
>
> (not sure if there is any maintainer to cc here, this is generic build
> infrastructure)
>
>> Andi Kleen writes:
>>
>> I wanted to ping this patch:
>>
>> https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658729.htm
Andi Kleen writes:
PING^3
> Andi Kleen writes:
>
> PING^2 for https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658602.html
>
> This fixes some musttail related test suite failures that cause noise on
> various targets.
>
>> Andi Kleen writes:
>>
>> I wanted to ping this patch. It fixes test
---
htdocs/gcc-15/changes.html | 7 +++
1 file changed, 7 insertions(+)
diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html
index edce138e..7c372688 100644
--- a/htdocs/gcc-15/changes.html
+++ b/htdocs/gcc-15/changes.html
@@ -123,6 +123,13 @@ a work-in-progress.
+AMD Ra
On Linux/x86_64,
464067a242150628ceb0d47daf2297f29a31743c is the first bad commit
commit 464067a242150628ceb0d47daf2297f29a31743c
Author: Richard Biener
Date: Mon May 13 14:57:01 2024 +0200
lower SLP load permutation to interleaving
caused
FAIL: gcc.dg/vect/slp-11a.c -flto -ffat-lto-obje
Hi!
The following testcase is miscompiled, because
get_member_function_from_ptrfunc
emits something like
(((FUNCTION.__pfn & 1) != 0)
? ptr + FUNCTION.__delta + FUNCTION.__pfn - 1
: FUNCTION.__pfn) (ptr + FUNCTION.__delta, ...)
or so, so FUNCTION tree is used there 5 times. There is
if (TREE_SI
As Jovan pointed out in pr115921, we're not reassociating expressions
like this on rv64:
(x & 0x3e) << 12
It generates something like this:
li a5,258048
sllia0,a0,12
and a0,a0,a5
We have a pattern that's designed to clean this up. Essentially
reassoci
Hi!
The following testcase is miscompiled. The problem is in the last_ovf step.
The second operand has signed _BitInt(513) type but has the MSB clear,
so range_to_prec returns 512 for it (i.e. it fits into unsigned
_BitInt(512)). Because of that the last step actually doesn't need to get
the mos
Hi Richard,
Am 02.09.24 um 13:58 schrieb Richard Biener:
Hmm, I can't really follow how and where it's currently decided whether to
output offload tables for the LTRANS units
Before the patch, output_offload_tables is called unconditionally, but
guarded by the check whether there is anything
On Mon, Aug 26, 2024 at 02:42:31PM +0800, Haochen Jiang wrote:
> * match.pd: Optimize (and ordered non-equal) to
> (not (or unordered equal))
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/optimize_one.c: New test.
The testcase FAILs on i686-linux, because it uses -mfpmath
On Mon, Sep 2, 2024 at 11:20 AM Jakub Jelinek wrote:
>
> On Mon, Aug 26, 2024 at 02:42:31PM +0800, Haochen Jiang wrote:
> > * match.pd: Optimize (and ordered non-equal) to
> > (not (or unordered equal))
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/i386/optimize_one.c: N
This time with the RISC-V marker so the pre-commit testing system will
pick it up...
Forwarded Message
Subject: [to-be-committed] [PR target/115921] Improve reassociation for rv64
Date: Mon, 2 Sep 2024 11:53:44 -0600
From: Jeff Law
To: gcc-patches@gcc.gnu.org
As Jovan po
On Mon, Sep 2, 2024 at 6:12 AM Evgeny Karpov
wrote:
>
> The anchors have been disabled as they use symbol + offset, which is
> not applicable for COFF AArch64.
This does not make sense to me at all. Anchors are a small
optimization to group together some static decls so that you could
reuse an an
On Mon, Sep 02, 2024 at 11:25:36AM -0700, Andrew Pinski wrote:
> On Mon, Sep 2, 2024 at 11:20 AM Jakub Jelinek wrote:
> >
> > On Mon, Aug 26, 2024 at 02:42:31PM +0800, Haochen Jiang wrote:
> > > * match.pd: Optimize (and ordered non-equal) to
> > > (not (or unordered equal))
> > >
> >
пн, 2 сент. 2024 г. в 12:10, Georg-Johann Lay :
>
> Am 02.09.24 um 09:18 schrieb Jan Dubiec:
> > On 02.09.2024 08:49, Georg-Johann Lay wrote:
> >> Atmel is no more the AVR manufacturer. This patch removes the
> >> manufacturer from the file headers.
> >>
> >> Ok for trunk?
> > In this context, mic
For x86-64, the context selector matching is are currently based on
features. That's obvious for 'SSE2' where any system offering SSE2
matches, but that also the case for, e.g. a selector asking for 'i486' –
which matches when compiling for 'i486', 'i586' and 'i686'.
That has pro and cons. Ass
On Mon, Sep 2, 2024 at 11:54 AM Jeff Law wrote:
>
> This time with the RISC-V marker so the pre-commit testing system will
> pick it up...
Hi Jeff,
Just a meta-note about precommit:
If the patch contains riscv or risc-v anywhere in the patch file pre commit
will run [1]. You can also cc patchw
On Mon, 2 Sep 2024, Evgeny Karpov wrote:
aarch64.cc has been updated to prevent emitting "symbol + offset"
for SYMBOL_SMALL_ABSOLUTE for the PECOFF target. "symbol + offset"
cannot be used in relocations for aarch64-w64-mingw32 due to
relocation requirements.
What relocation requirements are t
On Mon, 2 Sep 2024, Evgeny Karpov wrote:
The patch adds support for weak references. The original MinGW
implementation targets ix86, which handles weak symbols differently
compared to AArch64.
Please clarify this statement.
There is no difference between architectures with respect to how weak
Improve handling of constants where its upper and lower 32-bit
halves are the same and have negative values.
e.g. for:
unsigned long f (void) { return 0xf0f0f0f0f0f0f0f0UL; }
Without the patch:
li a0,-252645376
addia0,a0,240
li a5,-252645376
addia5,a5,241
sllia5,a5,32
add
Improve handling of large constants in riscv_build_integer, generate
better code for constants where the high half can be constructed
by shifting/shiftNadding the low half or if the halves differ by less
than 2k.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_build_integer): Detect new case
Improve handling of constants where the high half can be constructed by
inverting the lower half.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_build_integer): Detect constants
were the higher half is the lower half inverted.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/syn
Jie Mei 于2024年7月26日周五 14:50写道：
>
> This patch adds some floating point instructiions from mips32r6,
> for instance, MINA/MAXA.fmt, RINT.fmt, CLASS.fmt etc.
>
> Also add built-in functions to MIPSr6 to better handle tests
> for MIPSr6.
>
> gcc/ChangeLog:
>
> * config/mips/i6400.md (i6400_fp
As each AVX10.2 testcases previously, this is caused by option combination
warning,
which is expected.
> From: haochen.jiang
> Sent: Monday, September 2, 2024 9:06 PM
>
> On Linux/x86_64,
>
> f77435aa3911c437cba71991509eee57b333b3ce is the first bad commit commit
> f77435aa3911c437cba71991509e
On Mon, Sep 2, 2024 at 4:33 PM Levy Hsu wrote:
>
> Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
> Ok for trunk?
>
> This patch introduces new mode iterators and expands for the i386
> architecture to support partial vectorization of bf16 operations using
> AVX10.2 instructions. Thes
On Mon, Sep 2, 2024 at 4:42 PM Levy Hsu wrote:
>
> Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
> Ok for trunk?
Ok.
>
> This patch supports sminmax for partial vectorized V2BF/V4BF.
>
> gcc/ChangeLog:
>
> * config/i386/mmx.md (3): New define_expand for
> V2BF/V4BFsmaxmin
>
>
> -Original Message-
> From: Prathamesh Kulkarni
> Sent: Thursday, August 22, 2024 7:41 PM
> To: Richard Biener
> Cc: Richard Sandiford ; Thomas Schwinge
> ; gcc-patches@gcc.gnu.org
> Subject: RE: Re-compute TYPE_MODE and DECL_MODE while streaming in for
> accelerator
>
> External emai
On Tue, Sep 3, 2024 at 9:45 AM Jiang, Haochen via Gcc-regression
wrote:
>
> As each AVX10.2 testcases previously, this is caused by option combination
> warning,
> which is expected.
>
Can we put the warning for mix usage of mavx10 and -mavx512f under -Wpsabi
And add -Wno-psabi in addition to -ma
> -Original Message-
> From: Hongtao Liu
> Sent: Tuesday, September 3, 2024 1:47 PM
> To: Jiang, Haochen
> Cc: haochen.jiang ; ad...@levyhsu.com; gcc-
> regress...@gcc.gnu.org; gcc-patches@gcc.gnu.org
> Subject: Re: [r15-3359 Regression] FAIL: gcc.target/i386/avx10_2-bf-vector-
> cmpp-1
> -Original Message-
> From: Jakub Jelinek
> Sent: Tuesday, September 3, 2024 2:56 AM
> To: Andrew Pinski
> Cc: Jiang, Haochen ; Richard Biener
> ; gcc-patches@gcc.gnu.org; Liu, Hongtao
> ; ubiz...@gmail.com; Hu, Lin1
> Subject: Re: [PATCH 2/8] i386: Optimize ordered and nonequal
>
> On
Hi all,
The intrin for non-optimized got a typo in mask type, which will cause
the high bits of __mmask32 being unexpectedly zeroed.
The test does not fail under O0 with current 1b since the testcase is
wrong. We need to include avx512-mask-type.h after SIZE is defined, or
it will always be __mma
On Tue, Sep 3, 2024 at 7:36 AM Jiang, Haochen wrote:
>
>
>
> > -Original Message-
> > From: Hongtao Liu
> > Sent: Tuesday, September 3, 2024 1:47 PM
> > To: Jiang, Haochen
> > Cc: haochen.jiang ; ad...@levyhsu.com; gcc-
> > regress...@gcc.gnu.org; gcc-patches@gcc.gnu.org
> > Subject: Re:
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