The patch adds a new instruction pattern to handle conditional branches with
equality checks between shifted arithmetic operands. This pattern optimizes the
use of shifted constants (with trailing zeros), making it more efficient.
For the C code:
void f5(long long a) {
if ((a & 0x2120000) == 0x2000000)
g();
}
before the patch, the assembly code was:
f5:
li a5,34734080
and a0,a0,a5
li a5,33554432
beq a0,a5,.L21
ret
and after the patch the assembly is:
f5:
srli a5,a0,17
andi a5,a5,265
li a4,256
beq a5,a4,.L21
ret
Tested on both RV32 and RV64 with no regressions.
2024-09-02 Jovan Vukic <jovan.vu...@rt-rk.com>
gcc/ChangeLog:
PR target/113248
* config/riscv/riscv.md (*branch<ANYI:mode>_shiftedarith_equals_shifted):
New pattern.
gcc/testsuite/ChangeLog:
PR target/113248
* gcc.target/riscv/branch-1.c: Additional tests.
---
gcc/config/riscv/riscv.md | 32 +++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/branch-1.c | 16 +++++++++---
2 files changed, 45 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 3289ed2155a..c98a66dbc7c 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3126,6 +3126,38 @@
}
[(set_attr "type" "branch")])
+(define_insn_and_split "*branch<ANYI:mode>_shiftedarith_equals_shifted"
+ [(set (pc)
+ (if_then_else (match_operator 1 "equality_operator"
+ [(and:ANYI (match_operand:ANYI 2 "register_operand" "r")
+ (match_operand 3 "shifted_const_arith_operand" "i"))
+ (match_operand 4 "shifted_const_arith_operand" "i")])
+ (label_ref (match_operand 0 "" ""))
+ (pc)))
+ (clobber (match_scratch:X 5 "=&r"))
+ (clobber (match_scratch:X 6 "=&r"))]
+ "!SMALL_OPERAND (INTVAL (operands[3]))
+ && !SMALL_OPERAND (INTVAL (operands[4]))"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 5) (lshiftrt:X (subreg:X (match_dup 2) 0) (match_dup 8)))
+ (set (match_dup 5) (and:X (match_dup 5) (match_dup 9)))
+ (set (match_dup 6) (match_dup 10))
+ (set (pc) (if_then_else (match_op_dup 1 [(match_dup 5) (match_dup 6)])
+ (label_ref (match_dup 0)) (pc)))]
+{
+ HOST_WIDE_INT mask1 = INTVAL (operands[3]);
+ HOST_WIDE_INT mask2 = INTVAL (operands[4]);
+ int trailing = (ctz_hwi (mask1) > ctz_hwi (mask2))
+ ? ctz_hwi (mask2)
+ : ctz_hwi (mask1);
+
+ operands[8] = GEN_INT (trailing);
+ operands[9] = GEN_INT (mask1 >> trailing);
+ operands[10] = GEN_INT (mask2 >> trailing);
+}
+[(set_attr "type" "branch")])
+
(define_insn_and_split "*branch<ANYI:mode>_shiftedmask_equals_zero"
[(set (pc)
(if_then_else (match_operator 1 "equality_operator"
diff --git a/gcc/testsuite/gcc.target/riscv/branch-1.c
b/gcc/testsuite/gcc.target/riscv/branch-1.c
index b4a3a946379..e09328fe705 100644
--- a/gcc/testsuite/gcc.target/riscv/branch-1.c
+++ b/gcc/testsuite/gcc.target/riscv/branch-1.c
@@ -28,10 +28,20 @@ void f4(long long a)
g();
}
+void f5(long long a) {
+ if ((a & 0x2120000) == 0x2000000)
+ g();
+}
+
+void f6(long long a) {
+ if ((a & 0x70000000) == 0x30000000)
+ g();
+}
+
/* { dg-final { scan-assembler-times "slli\t" 2 } } */
-/* { dg-final { scan-assembler-times "srli\t" 3 } } */
-/* { dg-final { scan-assembler-times "andi\t" 1 } } */
-/* { dg-final { scan-assembler-times "\tli\t" 1 } } */
+/* { dg-final { scan-assembler-times "srli\t" 5 } } */
+/* { dg-final { scan-assembler-times "andi\t" 3 } } */
+/* { dg-final { scan-assembler-times "\tli\t" 3 } } */
/* { dg-final { scan-assembler-not "addi\t" } } */
/* { dg-final { scan-assembler-not "and\t" } } */
--
2.43.0
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