Re: [RFC 1/2] libbacktrace: add FDPIC support

Hi, Ian I believe that this patch broke bootstrap on AIX: /nasfarm/edelsohn/src/src/libbacktrace/xcoff.c: In function 'xcoff_add': /nasfarm/edelsohn/src/src/libbacktrace/xcoff.c:1309:40: error: incompatible type for argument 2 of 'backtrace_dwarf_add' 1309 | if (!backtrace_dwarf_add (state

Re: [PATCH ver 2] rs6000, update effective target for tests builtins-10*.c and, vec_perm-runnable-i128.c

On 7/16/24 6:19 PM, Carl Love wrote: > use __int128 types that are not supported on all platforms.  The > __int128 type is only supported on 64-bit platforms.  Need to check that > the platform is 64-bits and support the __int128 type.  Add the int128 and > lp64 flags to the target test. The test

[PATCH] RISC-V: Fix testcase missing arch attribute

The C + F extentions implies the zcf extension on rv32. Add missing zcf extension for the rv32 target. gcc/testsuite/ChangeLog: * gcc.target/riscv/target-attr-16.c: Update expected assembly Signed-off-by: Edwin Lu --- gcc/testsuite/gcc.target/riscv/target-attr-16.c | 2 +- 1 file chang

[PATCH] [x86][avx512] Optimize maskstore when mask is 0 or -1 in UNSPEC_MASKMOV

Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ready push to trunk. gcc/ChangeLog: PR target/115843 * config/i386/predicates.md (const0_or_m1_operand): New predicate. * config/i386/sse.md (*_store_mask_1): New pre_reload define_insn_and_split.

Re: [RFC 1/2] libbacktrace: add FDPIC support

On Tue, Jul 16, 2024 at 5:41 PM David Edelsohn wrote: > > I believe that this patch broke bootstrap on AIX: > > /nasfarm/edelsohn/src/src/libbacktrace/xcoff.c: In function 'xcoff_add': > /nasfarm/edelsohn/src/src/libbacktrace/xcoff.c:1309:40: error: incompatible > type for argument 2 of 'backtrac

Re: [PATCH] RISC-V: Fix testcase missing arch attribute

On Wed, Jul 17, 2024 at 3:15 AM Edwin Lu wrote: > > The C + F extentions implies the zcf extension on rv32. Add missing zcf > extension for the rv32 target. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/target-attr-16.c: Update expected assembly > > Signed-off-by: Edwin Lu > --- >

Re: [committed][PR rtl-optimization/115876][PR rtl-optimization/115916] Fix sign/carry bit handling in ext-dce

On Jul 15 2024, Jeff Law wrote: > My change to fix a ubsan issue broke handling propagation of the > carry/sign bit down through a right shift. What about the other ASHIFTs? -- Andreas Schwab, sch...@linux-m68k.org GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1 "And no

Re: [PATCH] [x86][avx512] Optimize maskstore when mask is 0 or -1 in UNSPEC_MASKMOV

On Wed, Jul 17, 2024 at 3:27 AM liuhongt wrote: > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. > Ready push to trunk. > > gcc/ChangeLog: > > PR target/115843 > * config/i386/predicates.md (const0_or_m1_operand): New > predicate. > * config/i386/sse.md

RE: [PATCH] [x86][avx512] Optimize maskstore when mask is 0 or -1 in UNSPEC_MASKMOV

> -Original Message- > From: Uros Bizjak > Sent: Wednesday, July 17, 2024 2:52 PM > To: Liu, Hongtao > Cc: gcc-patches@gcc.gnu.org; crazy...@gmail.com; hjl.to...@gmail.com > Subject: Re: [PATCH] [x86][avx512] Optimize maskstore when mask is 0 or -1 > in UNSPEC_MASKMOV > > On Wed, Jul 1

[RFC/RFA][PATCH 0/2] SVE intrinsics: Add strength reduction for division by constant.

This patch series is part of an ongoing effort to replace the SVE intrinsic svdiv by lower-strength instructions for division by constant. To that end, we implemented svdiv_impl::fold to perform the following transformation in gimple: - Division where all divisors are the same power of 2 --> svasr

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