[PATCH] Fix Xcode 16 build break with NULL != nullptr

From: Daniel Bertalan As of Xcode 16 beta 2 with the macOS 15 SDK, each re-inclusion of the stddef.h header causes the NULL macro in C++ to be re-defined to an integral constant (__null). This makes the workaround in d59a576b8 ("Redefine NULL to nullptr") ineffective, as other headers that are ty

Re: [PATCH] Fix Xcode 16 build break with NULL != nullptr

On Wed, 2024-07-10 at 06:59 +, d...@danielbertalan.dev wrote: > diff --git a/gcc/value-pointer-equiv.cc b/gcc/value-pointer-equiv.cc > index bfc940ec9915..f8564536c308 100644 > --- a/gcc/value-pointer-equiv.cc > +++ b/gcc/value-pointer-equiv.cc > @@ -62,7 +62,7 @@ public: >  private: >    auto_

Re: [PATCH] [alpha] adjust MEM alignment for block move [PR115459] (was: Re: [PATCH v2] [PR100106] Reject unaligned subregs when strict alignment is required)

On Thu, Jun 13, 2024 at 9:37 AM Alexandre Oliva wrote: > > Hello, Maciej, > > On Jun 12, 2024, "Maciej W. Rozycki" wrote: > > > This has regressed building the `alpha-linux-gnu' target, in libada, as > > from commit d6b756447cd5 including GCC 14 and up to current GCC 15 trunk: > > > | Error dete

Re: [PATCH] testsuite: Tests the pattern folding x/sqrt(x) to sqrt(x) for Float16

Hi Jennifer, > On 9 Jul 2024, at 14:07, Jennifer Schmitz wrote: > > As a follow-up to adding a pattern that folds x/sqrt(x) to sqrt(x) in > match.pd, this patch adds a test case for type Float16 for armv8.2-a+fp16. > > The patch was bootstrapped and regtested on aarch64-linux-gnu, no regressio

Re: [PATCH] testsuite: Tests the pattern folding x/sqrt(x) to sqrt(x) for Float16

Jennifer Schmitz writes: > As a follow-up to adding a pattern that folds x/sqrt(x) to sqrt(x) in > match.pd, this patch adds a test case for type Float16 for armv8.2-a+fp16. > > The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression. > Ok for mainline? > > Signed-off-by: Jen

Re: [PATCH] testsuite: Tests the pattern folding x/sqrt(x) to sqrt(x) for Float16

Richard Sandiford writes: > Jennifer Schmitz writes: >> As a follow-up to adding a pattern that folds x/sqrt(x) to sqrt(x) in >> match.pd, this patch adds a test case for type Float16 for armv8.2-a+fp16. >> >> The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression. >> Ok fo

[PATCH] middle-end: Fix stalled swapped condition code value [PR115836]

emit_store_flag_1 calculates scode (swapped condition code) at the beginning of the function from the value of code variable. However, code variable may change before scode usage site, resulting in invalid stalled scode value. Move calculation of scode value just before its only usage site to avo

Re: Re: [PATCH] [RISC-V] c implies zca, and conditionally zcf & zcd

On 2024-07-09 23:28  Jeff Law wrote: > > > >On 7/9/24 1:10 AM, Fei Gao wrote: >> According to Zc-1.0.4-3.pdf from >> https://github.com/riscvarchive/riscv-code-size-reduction/releases/tag/v1.0.4-3 >> The rule is that: >> - C always implies Zca >> - C+F implies Zcf (RV32 only) >> - C+D implies Zcd

Re: [PATCH V4] report message for operator %a on unaddressible operand

Hi Jeff, on 2024/6/5 16:30, Jiufu Guo wrote: > Hi, > > For PR96866, when printing asm code for modifier "%a", an addressable > operand is required. While the constraint "X" allow any kind of > operand even which is hard to get the address directly. e.g. extern > symbol whose address is in TOC. >

Re: [PATCH] Fix Xcode 16 build break with NULL != nullptr

On Wed, Jul 10, 2024 at 9:00 AM wrote: > > From: Daniel Bertalan > > As of Xcode 16 beta 2 with the macOS 15 SDK, each re-inclusion of the > stddef.h header causes the NULL macro in C++ to be re-defined to an > integral constant (__null). This makes the workaround in d59a576b8 > ("Redefine NULL t

Re: [PATCH] testsuite: Tests the pattern folding x/sqrt(x) to sqrt(x) for Float16

On Wed, 10 Jul 2024, Richard Sandiford wrote: > Richard Sandiford writes: > > Jennifer Schmitz writes: > >> As a follow-up to adding a pattern that folds x/sqrt(x) to sqrt(x) in > >> match.pd, this patch adds a test case for type Float16 for armv8.2-a+fp16. > >> > >> The patch was bootstrapped

Re: [PATCH] middle-end: Fix stalled swapped condition code value [PR115836]

On Wed, 10 Jul 2024, Uros Bizjak wrote: > emit_store_flag_1 calculates scode (swapped condition code) at the > beginning of the function from the value of code variable. However, > code variable may change before scode usage site, resulting in > invalid stalled scode value. > > Move calculation

[PATCH] rs6000: Escalate warning to error for VSX with explicit no-altivec etc.

Hi, As the discussion in PR115688, for now when users specify -mvsx and -mno-altivec explicitly, compiler emits warning rather than error, but considering both options are given explicitly, emitting hard error should be better. So this patch is to escalate some related warning to error when both

[PATCH] rs6000: Consider explicitly set options in target option parsing [PR115713]

Hi, In rs6000_inner_target_options, when enabling VSX we enable altivec and disable -mavoid-indexed-addresses implicitly, but it doesn't consider the case that the options altivec and avoid-indexed-addresses can be explicitly disabled. As the test case in PR115713#c1 shows, with target attribute

[PATCH] rs6000: Update option set in rs6000_inner_target_options [PR115713]

Hi, When function rs6000_inner_target_options parsing target options, it updates the explicit option set information for rs6000_opt_masks by rs6000_isa_flags_explicit, but it misses to update that information for rs6000_opt_vars, and it can result in some unexpected consequence as the associated t

Ping^5 [PATCH] add rlwinm pattern for DImode for constant building

Hi, Gentle ping... BR, Jeff(Jiufu) Guo Jiufu Guo writes: > Hi, > > Gentle ping. > > BR, > Jeff(Jiufu) Guo > > Jiufu Guo writes: > >> Hi, >> >> Gentle ping ... >> >> Jiufu Guo writes: >> >>> Hi, >>> >>> Gentle ping ... >>> >>> BR, >>> Jeff(Jiufu) Guo >>> >>> Jiufu Guo writes: >>> Hi,

Re: [Fortran, Patch, PR 96992, V4] Fix Class arrays of different ranks are rejected as storage association argument

Hi Harald, thanks for the review. I totally agree, that this patch has gotten bigger than I expected (and wanted). But things are as they are. About the coding style: I have worked in so many projects, that I consider a consistent coding style luxury. I esp. do not have my own one anymore. The fo

Re: [PATCH V4] report message for operator %a on unaddressible operand

Hi, "Kewen.Lin" writes: > Hi Jeff, > > on 2024/6/5 16:30, Jiufu Guo wrote: >> Hi, >> >> For PR96866, when printing asm code for modifier "%a", an addressable >> operand is required. While the constraint "X" allow any kind of >> operand even which is hard to get the address directly. e.g. ext

Re: [RFC] Proposal to support Packed Boolean Vector masks.

On 7/9/24 4:22 PM, Richard Biener wrote: On Tue, Jul 9, 2024 at 11:45 AM Tejas Belagod wrote: On 7/8/24 4:45 PM, Richard Biener wrote: On Mon, Jul 8, 2024 at 11:27 AM Tejas Belagod wrote: Hi, Sorry to have dropped the ball on https://gcc.gnu.org/pipermail/gcc-patches/2023-July/625535.html

[PATCH 1/3] lower SLP load permutation to interleaving

The following emulates classical interleaving for SLP load permutes that we are unlikely handling natively. This is to handle cases where interleaving (or load/store-lanes) is the optimal choice for vectorizing even when we are doing that within SLP. An example would be void foo (int * __restric

[PATCH 2/3] Support group-size of three in SLP load permutation lowering

The following adds support for group-size three in SLP load permutation lowering to match the non-SLP capabilities. This is done by using the non-interleaving fallback code which then creates at VF == 4 from { { a0, b0, c0 }, { a1, b1, c1 }, { a2, b2, c2 }, { a3, b3, c3 } } the intermediate vector

[PATCH 3/3] RISC-V: load and store-lanes with SLP

The following is a prototype for how to represent load/store-lanes within SLP. I've for now settled with having a single load node with multiple permute nodes acting as selection, one for each loaded lane and a single store node fed from all stored lanes. For for (int i = 0; i < 1024; ++i)

Re: [patch,avr] PR115830: Improve code by using more condition code

Am 10.07.24 um 01:17 schrieb Jeff Law: On 7/9/24 4:03 AM, Georg-Johann Lay wrote: Hi Jeff, This patch adds peephole2s and insns to make better use of instructions that set condition code (SREG) as a byproduct. Of course with cc0 all this was *much* simpler... so here we go; adding CCNmode and

Re: [RFC] Proposal to support Packed Boolean Vector masks.

On Wed, Jul 10, 2024 at 10:49 AM Tejas Belagod wrote: > > On 7/9/24 4:22 PM, Richard Biener wrote: > > On Tue, Jul 9, 2024 at 11:45 AM Tejas Belagod wrote: > >> > >> On 7/8/24 4:45 PM, Richard Biener wrote: > >>> On Mon, Jul 8, 2024 at 11:27 AM Tejas Belagod > >>> wrote: > > Hi, > >>>

PR115394: Remove streamer_debugging and it's uses

Hi Richard, As per your suggestion in PR, the attached patch removes streamer_debugging and it's uses. Bootstrapped on aarch64-linux-gnu. OK to commit ? Signed-off-by: Prathamesh Kulkarni Thanks, Prathamesh [PR115394] Remove streamer_debugging and it's uses. gcc/ChangeLog: PR lto/11539

[Fortran, Patch, PR78466, coarray, v1] Fix Explicit cobounds of a procedures parameter not respected

Hi all, the attached patch fixes explicit cobounds of procedure parameters not respected. The central issue is, that class (array) types store their attributes and `as` in the first component of the derived type. This made comparison of existing types harder and gfortran confused generated trees f

Re: PR115394: Remove streamer_debugging and it's uses

On Wed, 10 Jul 2024, Prathamesh Kulkarni wrote: > Hi Richard, > As per your suggestion in PR, the attached patch removes streamer_debugging > and it's uses. > Bootstrapped on aarch64-linux-gnu. > OK to commit ? OK. Thanks, Richard. > Signed-off-by: Prathamesh Kulkarni > > Thanks, > Prathames

Re: [PATCH v1] Match: Support form 2 for the .SAT_TRUNC

On Fri, Jul 5, 2024 at 2:48 PM wrote: > > From: Pan Li > > This patch would like to add form 2 support for the .SAT_TRUNC. Aka: > > Form 2: > #define DEF_SAT_U_TRUC_FMT_2(NT, WT) \ > NT __attribute__((noinline)) \ > sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \ > {

[PATCH v1] Vect: Promote unsigned .SAT_ADD constant operand for vectorizable_call

From: Pan Li The .SAT_ADD has 2 operand and one of the operand may be INTEGER_CST. For example _1 = .SAT_ADD (_2, 9) comes from below sample code. Form 3: #define DEF_VEC_SAT_U_ADD_IMM_FMT_3(T, IMM) \ T __attribute__((noinline))

Re: [RFC] Proposal to support Packed Boolean Vector masks.

On 7/10/24 2:38 PM, Richard Biener wrote: On Wed, Jul 10, 2024 at 10:49 AM Tejas Belagod wrote: On 7/9/24 4:22 PM, Richard Biener wrote: On Tue, Jul 9, 2024 at 11:45 AM Tejas Belagod wrote: On 7/8/24 4:45 PM, Richard Biener wrote: On Mon, Jul 8, 2024 at 11:27 AM Tejas Belagod wrote: Hi

Re: [PATCH] gimple ssa: Teach switch conversion to optimize powers of 2 switches

On Mon, 8 Jul 2024, Filip Kastl wrote: > Hi, > > I'm replying to Richard and keeping Andrew in cc since your suggestions > overlap. > > > On Tue 2024-06-11 14:48:06, Richard Biener wrote: > > On Thu, 30 May 2024, Filip Kastl wrote: > > > +/* { dg-do compile } */ > > > +/* { dg-options "-O2 -fdu

Re: [PATCH] c++, contracts: Fix ICE in create_tmp_var [PR113968]

On Tue, 9 Jul 2024 at 22:50, Jason Merrill wrote: > On 7/9/24 6:41 AM, Nina Dinka Ranns wrote: > > On Mon, 8 Jul 2024 at 16:01, Jason Merrill > > wrote: > > > > On 7/8/24 7:47 AM, Nina Dinka Ranns wrote: > > > HI Jason, > > > > > > On Fri, 5 Jul 2024 a

[PATCH v2] Fix Xcode 16 build break with NULL != nullptr

As of Xcode 16 beta 2 with the macOS 15 SDK, each re-inclusion of the stddef.h header causes the NULL macro in C++ to be re-defined to an integral constant (__null). This makes the workaround in d59a576b8 ("Redefine NULL to nullptr") ineffective, as other headers that are typically included after s

[PATCH] RISC-V: c implies zca, and conditionally zcf & zcd

According to Zc-1.0.4-3.pdf from https://github.com/riscvarchive/riscv-code-size-reduction/releases/tag/v1.0.4-3 The rule is that: - C always implies Zca - C+F implies Zcf (RV32 only) - C+D implies Zcd Signed-off-by: Fei Gao gcc/ChangeLog: * common/config/riscv/riscv-common.cc: c

RE: [PATCH][ivopts]: perform affine fold on unsigned addressing modes known not to overflow. [PR114932]

> -Original Message- > From: Richard Biener > Sent: Thursday, June 20, 2024 8:55 AM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd ; bin.ch...@linux.alibaba.com > Subject: RE: [PATCH][ivopts]: perform affine fold on unsigned addressing modes > known not to overflow. [PR114932] >

RE: [PATCH][ivopts]: use affine_tree when comparing IVs during candidate selection [PR114932]

> > > I might also point back to the idea I threw in somewhere, adding > > > OEP_VALUE (or a better name) to the set of flags accepted by > > > operand_equal_p. You mentioned hashing IIRC but I don't see the patches > > > touching hashing? > > > > > > > Yes, That can indeed be done with this appro

Re: [PATCH v2] Fix Xcode 16 build break with NULL != nullptr

Hello Daniel, Thanks for the patch! > On 10 Jul 2024, at 10:43, Daniel Bertalan wrote: > > As of Xcode 16 beta 2 with the macOS 15 SDK, each re-inclusion of the > stddef.h header causes the NULL macro in C++ to be re-defined to an > integral constant (__null). This makes the workaround in d59a5

Re: [RFC] Proposal to support Packed Boolean Vector masks.

Tejas Belagod writes: > On 7/10/24 2:38 PM, Richard Biener wrote: >> On Wed, Jul 10, 2024 at 10:49 AM Tejas Belagod wrote: >>> >>> On 7/9/24 4:22 PM, Richard Biener wrote: On Tue, Jul 9, 2024 at 11:45 AM Tejas Belagod wrote: > > On 7/8/24 4:45 PM, Richard Biener wrote: >>

RE: [PATCH v1] Match: Support form 2 for the .SAT_TRUNC

> OK. Committed, thanks Richard. Pan -Original Message- From: Richard Biener Sent: Wednesday, July 10, 2024 5:24 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com; tamar.christ...@arm.com; jeffreya...@gmail.com; rdapp@gmail.com; Liu, Hongtao

RE: [PATCH]middle-end: Implement conditonal store vectorizer pattern [PR115531]

> > > > > > > + } > > > > + > > > > + if (new_code == ERROR_MARK) > > > > + { > > > > + /* We couldn't flip the condition, so invert the mask > > > > instead. */ > > > > + itype = TREE_TYPE (cmp_ls); > > > > + conv = gimple_build_assign (var, BIT_XOR_EXPR,

[PATCH 2/2]AArch64: implement TARGET_VECTORIZE_CONDITIONAL_OPERATION_IS_EXPENSIVE [PR115531].

Hi All, This implements the new target hook indicating that for AArch64 when possible we prefer masked operations for any type vs doing LOAD + SELECT or SELECT + STORE. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: PR tree-

Re: [PATCH v2] Fix Xcode 16 build break with NULL != nullptr

On Wed, Jul 10, 2024 at 12:23 PM Iain Sandoe wrote: > > Hello Daniel, > > Thanks for the patch! > > > On 10 Jul 2024, at 10:43, Daniel Bertalan wrote: > > > > As of Xcode 16 beta 2 with the macOS 15 SDK, each re-inclusion of the > > stddef.h header causes the NULL macro in C++ to be re-defined to

Re: [RFC] Proposal to support Packed Boolean Vector masks.

On Wed, Jul 10, 2024 at 12:44 PM Richard Sandiford wrote: > > Tejas Belagod writes: > > On 7/10/24 2:38 PM, Richard Biener wrote: > >> On Wed, Jul 10, 2024 at 10:49 AM Tejas Belagod > >> wrote: > >>> > >>> On 7/9/24 4:22 PM, Richard Biener wrote: > On Tue, Jul 9, 2024 at 11:45 AM Tejas Bel

Lower zeroing array assignment to memset for allocatable arrays

Hi, The attached patch lowers zeroing array assignment to memset for allocatable arrays. For example: subroutine test(z, n) implicit none integer :: n real(4), allocatable :: z(:,:,:) allocate(z(n, 8192, 2048)) z = 0 end subroutine results in following call to memset instead

Re: [PATCH v3] Vect: Optimize truncation for .SAT_SUB operands

On Tue, Jul 9, 2024 at 6:03 AM wrote: > > From: Pan Li > > To get better vectorized code of .SAT_SUB, we would like to avoid the > truncated operation for the assignment. For example, as below. > > unsigned int _1; > unsigned int _2; > unsigned short int _4; > _9 = (unsigned short int).SAT_SUB

Re: [match.pd PATCH] PR tree-optimization/114661: Generalize MULT_EXPR recognition.

On Wed, Jul 10, 2024 at 12:28 AM Roger Sayle wrote: > > > This patch resolves PR tree-optimization/114661, by generalizing the set > of expressions that we canonicalize to multiplication. This extends the > optimization(s) contributed (by me) back in July 2021. > https://gcc.gnu.org/pipermail/gcc

Re: [PATCH v1] Vect: Promote unsigned .SAT_ADD constant operand for vectorizable_call

On Wed, Jul 10, 2024 at 11:28 AM wrote: > > From: Pan Li > > The .SAT_ADD has 2 operand and one of the operand may be INTEGER_CST. > For example _1 = .SAT_ADD (_2, 9) comes from below sample code. > > Form 3: > #define DEF_VEC_SAT_U_ADD_IMM_FMT_3(T, IMM) \ > T __attri

[PATCH] aarch64: Avoid alloca in target attribute parsing

The handling of the target attribute used alloca to allocate a copy of unverified user input, which could exhaust the stack if the input is too long. This patch converts it to auto_vecs instead. I wondered about converting it to use std::string, which we already use elsewhere, but that would be m

RE: [PATCH 2/3] Support group-size of three in SLP load permutation lowering

> -Original Message- > From: Richard Biener > Sent: Wednesday, July 10, 2024 10:04 AM > To: gcc-patches@gcc.gnu.org > Subject: [PATCH 2/3] Support group-size of three in SLP load permutation > lowering > > The following adds support for group-size three in SLP load permutation > lowering

Re: [PATCH 2/2]AArch64: implement TARGET_VECTORIZE_CONDITIONAL_OPERATION_IS_EXPENSIVE [PR115531].

Tamar Christina writes: > Hi All, > > This implements the new target hook indicating that for AArch64 when possible > we prefer masked operations for any type vs doing LOAD + SELECT or > SELECT + STORE. > > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. > > Ok for master? > > Than

[committed] arm: cleanup legacy ARM_PE code

The arm 'pe' target was removed back in 2012 when the FPA support was removed, but in a small number of places some conditional code was accidentally left behind. It's no-longer needed, so remove it. gcc/ChangeLog: * config/arm/arm-protos.h (arm_dllexport_name_p): Remove prototype.

[PING^3][PATCH v2] docs: Update function multiversioning documentation

On Mon, Jun 10, 2024 at 05:08:21PM +0100, Andrew Carlotti wrote: > > On Tue, Apr 30, 2024 at 05:10:45PM +0100, Andrew Carlotti wrote: > > Add target_version attribute to Common Function Attributes and update > > target and target_clones documentation. Move shared detail and examples > > to the

testsuite: Remove no_fsanitize_address install directory dependency

The current no_fsanitize_address effective target check (implemented in target-supports.exp rather than in asan.exp) has some problems with the link path. Because it is not called from in between asan_init and asan_finish the link paths of the compiler are not changed to point at the build directo

[PATCH] tree-optimization/115825 - improve unroll estimates for volatile accesses

The loop unrolling code assumes that one third of all volatile accesses can be possibly optimized away which is of course not true. This leads to excessive unrolling in some cases. The following tracks the number of stmts with side-effects as those are not eliminatable later and only assumes one

Re: [PATCH] Add gcc.gnu.org account names to MAINTAINERS

On Wed, Jul 10, 2024 at 12:36:15PM +0100, Richard Sandiford wrote: > The account names in the file were taken from a trawl of the > gcc-cvs archives, with a very small number of manual edits for > ambiguities. There are a handful of names that I couldn't find; > the new column has "-" for those.

Re: testsuite: Remove no_fsanitize_address install directory dependency

... Oops, just after sending I noticed that `check_effective_target_fsanitize_address_compilation` is caching its result under the same name as the original `check_effective_target_fsanitize_address` in `asan-dg.exp`. Attaching an updated patch (with updated cover letter) that adjusts the pro

Re: testsuite: Remove no_fsanitize_address install directory dependency

Hi Matthew, > The current no_fsanitize_address effective target check (implemented in > target-supports.exp rather than in asan.exp) has some problems with the > link path. > > Because it is not called from in between asan_init and asan_finish the > link paths of the compiler are not changed to po

RE: [PATCH 2/3] Support group-size of three in SLP load permutation lowering

On Wed, 10 Jul 2024, Tamar Christina wrote: > > -Original Message- > > From: Richard Biener > > Sent: Wednesday, July 10, 2024 10:04 AM > > To: gcc-patches@gcc.gnu.org > > Subject: [PATCH 2/3] Support group-size of three in SLP load permutation > > lowering > > > > The following adds su

[Fortran, Patch, PR82904] Fix [11/12/13/14/15 Regression][Coarray] ICE in make_ssa_name_fn, at tree-ssanames.c:261

Hi all, the patch attached fixes the use of an uninitialized variable for the string length in the declaration of the char[1:_len] type (the _len!). The type for save'd deferred length char arrays is now char*, so that there is no need for the length in the type declaration anymore. The length is

Re: [Fortran, Patch, PR82904] Fix [11/12/13/14/15 Regression][Coarray] ICE in make_ssa_name_fn, at tree-ssanames.c:261

On Wed, 10 Jul 2024, Andre Vehreschild wrote: > Hi all, > > the patch attached fixes the use of an uninitialized variable for the string > length in the declaration of the char[1:_len] type (the _len!). The type for > save'd deferred length char arrays is now char*, so that there is no need for >

[PATCH] fixincludes: add bypass to darwin_objc_runtime_1

The header that this fix applies to has been fixed in macOS 15 beta SDK. Therefore, we can include a bypass. Tested on aarch64-apple-darwin24. OK to push? FX 0001-fixincludes-add-bypass-to-darwin_objc_runtime_1.patch Description: Binary data

[PATCH 0/1] AArch64: LUTI2/LUTI4 ACLE for SVE2

From: Vladimir Miloserdov Hi All, This patch introduces support for LUTI2/LUTI4 ACLE for SVE2. LUTI instructions are used for efficient table lookups with 2-bit or 4-bit indices. LUTI2 reads indexed 8-bit or 16-bit elements from the low 128 bits of the table vector using packed 2-bit indices, w

[PATCH 1/1] AArch64: Add LUTI ACLE for SVE2

This patch introduces support for LUTI2/LUTI4 ACLE for SVE2. LUTI instructions are used for efficient table lookups with 2-bit or 4-bit indices. LUTI2 reads indexed 8-bit or 16-bit elements from the low 128 bits of the table vector using packed 2-bit indices, while LUTI4 can read from the low 128

[r15-1936 Regression] FAIL: gcc.target/i386/avx512vl-vpmovuswb-2.c execution test on Linux/x86_64

On Linux/x86_64, 80e446e829d818dc19daa6e671b9626e93ee4949 is the first bad commit commit 80e446e829d818dc19daa6e671b9626e93ee4949 Author: Pan Li Date: Fri Jul 5 20:36:35 2024 +0800 Match: Support form 2 for the .SAT_TRUNC caused FAIL: gcc.target/i386/avx512f-vpmovusqb-2.c execution test

Re: testsuite: Remove no_fsanitize_address install directory dependency

On 7/10/24 13:42, Rainer Orth wrote: N.b. one alternative would be to remove this effective target and try to move all tests which currently use this into directories which run their tests between calls to `asan_finish` and `asan_init`. This seems like it might ensure a clearer division of "asan

Re: Ping^3 [PATCH-1v3] Value Range: Add range op for builtin isinf

On Mon, 2024-07-01 at 09:11 +0800, HAO CHEN GUI wrote: > Hi, >   Gently ping it. > https://gcc.gnu.org/pipermail/gcc-patches/2024-May/653096.html I guess you can add PR114678 into the subject and the ChangeLog, and also mention the patch in the bugzilla. -- Xi Ruoyao School of Aerospace Scienc

RE: [PATCH]middle-end: Implement conditonal store vectorizer pattern [PR115531]

Sorry missed a review comment to change !DR_IS_WRITE into DR_IS_READ. Updated patch: Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: PR tree-optimization/115531 * tree-vect-patterns.cc (vect_cond_store_pattern_same_re

Re: Ping^3 [PATCH-1v3] Value Range: Add range op for builtin isinf

On Wed, 2024-07-10 at 21:54 +0800, Xi Ruoyao wrote: > On Mon, 2024-07-01 at 09:11 +0800, HAO CHEN GUI wrote: > > Hi, > >   Gently ping it. > > https://gcc.gnu.org/pipermail/gcc-patches/2024-May/653096.html > > I guess you can add PR114678 into the subject and the ChangeLog, and > also mention the

[PATCH 04/10] arm: Fix arm backend-use of (u|s|us)dot_prod patterns.

gcc/ChangeLog: * config/arm/arm-builtins.cc (enum arm_builtins): Add new ARM_BUILTIN_* enum values: SDOTV8QI, SDOTV16QI, UDOTV8QI, UDOTV16QI, USDOTV8QI, USDOTV16QI. (arm_init_dotprod_builtins): New. (arm_init_builtins): Add call to `arm_init_dotprod_builtins

[PATCH 01/10] optabs: Make all `*dot_prod_optab's modeled as conversions

Given the specification in the GCC internals manual defines the {u|s}dot_prod standard name as taking "two signed elements of the same mode, adding them to a third operand of wider mode", there is currently ambiguity in the relationship between the mode of the first two arguments and that of the th

[PATCH 10/10] autovectorizer: Test autovectorization of different dot-prod modes.

From: Victor Do Nascimento Given the novel treatment of the dot product optab as a conversion we are now able to target, for a given architecture, different relationships between output modes and input modes. This is made clearer by way of example. Previously, on AArch64, the following loop was

[PATCH 07/10] mips: Adjust dot-product backend patterns

Following the migration of the dot_prod optab from a direct to a conversion-type optab, ensure all back-end patterns incorporate the second machine mode into pattern names. gcc/ChangeLog: * config/mips/loongson-mmi.md (sdot_prodv4hi): Deleted. (sdot_prodv2siv4hi): New. --- gcc/co

[PATCH 09/10] c6x: Adjust dot-product backend patterns

Following the migration of the dot_prod optab from a direct to a conversion-type optab, ensure all back-end patterns incorporate the second machine mode into pattern names. gcc/ChangeLog: * config/c6x/c6x.md (sdot_prodv2hi): Deleted. (sdot_prodsiv2hi): New. --- gcc/config/c6x/c6x

[PATCH 08/10] altivec: Adjust dot-product backend patterns

Following the migration of the dot_prod optab from a direct to a conversion-type optab, ensure all back-end patterns incorporate the second machine mode into pattern names. gcc/ChangeLog: * config/rs6000/altivec.md (udot_prod): Deleted. (udot_prodv4si): New. (sdot_prodv8hi

[PATCH 02/10] autovectorizer: Add basic support for convert optabs

Given the shift from modeling dot products as direct optabs to treating them as conversion optabs, we make necessary changes to the autovectorizer code to ensure that given the relevant tree code, together with the input and output data modes, we can retrieve the relevant optab and subsequently the

[PATCH 06/10] arc: Adjust dot-product backend patterns

Following the migration of the dot_prod optab from a direct to a conversion-type optab, ensure all back-end patterns incorporate the second machine mode into pattern names. gcc/ChangeLog: * config/arc/simdext.md (sdot_prodv2hi): Deleted. (sdot_prodsiv2hi): New. (udot_prodv

[PATCH 05/10] i386: Fix dot_prod backend patterns for mmx and sse targets

Following the migration of the dot_prod optab from a direct to a conversion-type optab, ensure all back-end patterns incorporate the second machine mode into pattern names. gcc/ChangeLog: * config/i386/mmx.md (usdot_prodv8qi): Deleted. (usdot_prodv2siv8qi): New. (sdot_prod

[PATCH 00/10] Make `dot_prod' a convert-type optab

Given the specification in the GCC internals manual defines the {u|s}dot_prod standard name as taking "two signed elements of the same mode, adding them to a third operand of wider mode", there is currently ambiguity in the relationship between the mode of the first two arguments and that of the th

[PATCH 03/10] aarch64: Fix aarch64 backend-use of (u|s|us)dot_prod patterns.

Given recent changes to the dot_prod standard pattern name, this patch fixes the aarch64 back-end by implementing the following changes: 1. Add 2nd mode to all (u|s|us)dot_prod patterns in .md files. 2. Rewrite initialization and function expansion mechanism for simd builtins. 3. Fix all direct ca

Re: [PATCH] fixincludes: add bypass to darwin_objc_runtime_1

> On 10 Jul 2024, at 14:09, FX Coudert wrote: > > The header that this fix applies to has been fixed in macOS > 15 beta SDK. Therefore, we can include a bypass. shame it’s not fixed earlier :( > Tested on aarch64-apple-darwin24. OK to push? yes OK for tunk (and backports perhaps once mac

Re: mve: Fix vsetq_lane for 64-bit elements with lane 1 [PR 115611]

On 26/06/2024 13:20, Andre Vieira (lists) wrote: > This patch fixes the backend pattern that was printing the wrong input > scalar register pair when inserting into lane 1. > > Added a new test to force float-abi=hard so we can use scan-assembler to check > correct codegen. > > Regression tested

Re: [PATCH] fixincludes: add bypass to darwin_objc_runtime_1

Thanks, pushed as https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=8326956159053b215b5cfe6cd41bfceff413491e FX

Re: [PATCH] c++, contracts: Fix ICE in create_tmp_var [PR113968]

On 7/10/24 5:37 AM, Nina Dinka Ranns wrote: On Tue, 9 Jul 2024 at 22:50, Jason Merrill > wrote: On 7/9/24 6:41 AM, Nina Dinka Ranns wrote: > On Mon, 8 Jul 2024 at 16:01, Jason Merrill mailto:ja...@redhat.com> >

[PATCH] fixincludes: skip stdio_stdarg_h on darwin

I found another useless fixincludes on darwin, but this one was a bit harder to diagnose. GCC trunk applies a fix to on modern Darwin: it is stdio_stdarg_h. That fix is actually part of a pair, along with stdio_va_list, and they appear to work around issues with some old Unix (or BSD?) headers

[PATCH] recog: Handle some mode-changing hardreg propagations

insn_propagation would previously only replace (reg:M H) with X for some hard register H if the uses of H were also in mode M. This patch extends it to handle simple mode punning too. The original motivation was to try to get rid of the execution frequency test in aarch64_split_simd_shift_p, but d

Re: [PATCH] recog: Handle some mode-changing hardreg propagations

On 7/10/24 9:32 AM, Richard Sandiford wrote: insn_propagation would previously only replace (reg:M H) with X for some hard register H if the uses of H were also in mode M. This patch extends it to handle simple mode punning too. The original motivation was to try to get rid of the execution f

[PATCH] internal-fn: Reuse SUBREG_PROMOTED_VAR_P handling

expand_fn_using_insn has code to handle SUBREG_PROMOTED_VAR_P destinations. Specifically, for: (subreg/v:M1 (reg:M2 R) ...) it creates a new temporary register T, uses it for the output operand, then sign- or zero-extends the M1 lowpart of T to M2, storing the result in R. This patch splits t

Re: [PATCH] fixincludes: skip stdio_stdarg_h on darwin

Hi FX, > On 10 Jul 2024, at 16:25, FX Coudert wrote: > > I found another useless fixincludes on darwin, but this one was a bit harder > to diagnose. GCC trunk applies a fix to on modern Darwin: it is > stdio_stdarg_h. That fix is actually part of a pair, along with > stdio_va_list, and they

[PATCH] opts: allow -gctf, -gbtf, -gdwarf simultaneously

[This is a resend of a patch previously sent as: PATCH v4 6/6 opts: allow any combination of DWARF,CTF,BTF https://gcc.gnu.org/pipermail/gcc-patches/2024-June/654253.html] Previously it was not supported to generate both CTF and BTF debug info in the same compiler run, as both formats made i

Re: [PATCH] RISC-V: c implies zca, and conditionally zcf & zcd

On 7/10/24 4:12 AM, Fei Gao wrote: According to Zc-1.0.4-3.pdf from https://github.com/riscvarchive/riscv-code-size-reduction/releases/tag/v1.0.4-3 The rule is that: - C always implies Zca - C+F implies Zcf (RV32 only) - C+D implies Zcd Signed-off-by: Fei Gao gcc/ChangeLog: * common

Re: [PATCH] internal-fn: Reuse SUBREG_PROMOTED_VAR_P handling

On 7/10/24 9:44 AM, Richard Sandiford wrote: expand_fn_using_insn has code to handle SUBREG_PROMOTED_VAR_P destinations. Specifically, for: (subreg/v:M1 (reg:M2 R) ...) it creates a new temporary register T, uses it for the output operand, then sign- or zero-extends the M1 lowpart of T t

[PATCH] testsuite: Align testcase with implementation [PR105090]

Is this ok for the following branches? - trunk - releases/gcc-14 - releases/gcc-13 -- Since r13-1006-g2005b9b888eeac, the test case copysign_softfloat_1.c no longer contains any lsr istruction, so drop the check as per comment 9 in PR105090. gcc/testsuite/ChangeLog: PR target/105090

Re: [RFC/RFA] [PATCH 06/12] aarch64: Implement new expander for efficient CRC computation

Mariam Arutunian writes: > On Sat, Jun 8, 2024 at 3:41 PM Richard Sandiford > wrote: > >> Mariam Arutunian writes: >> > This patch introduces two new expanders for the aarch64 backend, >> > dedicated to generate optimized code for CRC computations. >> > The new expanders are designed to leverage

Re: [PATCH] testsuite: Align testcase with implementation [PR105090]

On 10/07/2024 17:26, Torbjörn SVENSSON wrote: > Is this ok for the following branches? > - trunk > - releases/gcc-14 > - releases/gcc-13 > > -- > > Since r13-1006-g2005b9b888eeac, the test case copysign_softfloat_1.c > no longer contains any lsr istruction, so drop the check as per > comment 9 in

Re: [PATCH] internal-fn: Reuse SUBREG_PROMOTED_VAR_P handling

Thanks for the review. Jeff Law writes: > On 7/10/24 9:44 AM, Richard Sandiford wrote: >> expand_fn_using_insn has code to handle SUBREG_PROMOTED_VAR_P >> destinations. Specifically, for: >> >>(subreg/v:M1 (reg:M2 R) ...) >> >> it creates a new temporary register T, uses it for the output

Re: [Committed V2 1/2] RISC-V: Add support for B standard extension

Committed! Edwin On 7/9/2024 12:07 PM, Jeff Law wrote: On 7/9/24 11:44 AM, Edwin Lu wrote: This patch adds support for recognizing the B standard extension to be the collection of Zba, Zbb, Zbs extensions for consistency and conciseness across toolchains * https://github.com/riscv/riscv-b

Re: [PATCH] testsuite: Align testcase with implementation [PR105090]

On 2024-07-10 18:41, Richard Earnshaw (lists) wrote: On 10/07/2024 17:26, Torbjörn SVENSSON wrote: Is this ok for the following branches? - trunk - releases/gcc-14 - releases/gcc-13 -- Since r13-1006-g2005b9b888eeac, the test case copysign_softfloat_1.c no longer contains any lsr istruction,

Re: [PATCH] internal-fn: Reuse SUBREG_PROMOTED_VAR_P handling

On 7/10/24 10:48 AM, Richard Sandiford wrote: Thanks for the review. Jeff Law writes: On 7/10/24 9:44 AM, Richard Sandiford wrote: expand_fn_using_insn has code to handle SUBREG_PROMOTED_VAR_P destinations. Specifically, for: (subreg/v:M1 (reg:M2 R) ...) it creates a new temporary r

[PATCH] PR 115800: Allow builds of little endian powerpc using --with-cpu=power5

The following two patches will allow GCC to be built with a little endian target where the default CPU is power5. In particular, both of the libstc++-v3 and libgfortran libraries assumeed that any little endian powerpc system would support IEEE 128-bit. However, to support IEEE 128-bit, you need

[PATCH 1/2] PR 115800: Fix libgfortran build using --with-cpu=power5

If you build a little endian compiler and select a default CPU of power5 (i.e. --with-cpu=power5), GCC cannot be built. The reason is that both the libgfortran and libstdc++-v3 libraries assume that all little endian powerpc builds support IEEE 128-bit floating point. However, if the default cpu

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