On 26/06/2024 13:20, Andre Vieira (lists) wrote: > This patch fixes the backend pattern that was printing the wrong input > scalar register pair when inserting into lane 1. > > Added a new test to force float-abi=hard so we can use scan-assembler to check > correct codegen. > > Regression tested arm-none-eabi with > -march=armv8.1-m.main+mve/-mfloat-abi=hard/-mfpu=auto > > gcc/ChangeLog: > > PR target/115611 > * config/arm/mve.md (mve_vec_setv2di_internal): Fix printing of input > scalar register pair when lane = 1. > > gcc/testsuite/ChangeLog: > > * gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c: New test.
OK. R.
