Re: [PATCH] RISC-V: Add the Zihpm and Zicntr extensions

I realized we missed this on trunk, and I need this on adding -mcpu for sfive cores, so I'm gonna push this to trunk. Most concerns are around the assembler stuff, so I believe it's less controversial on the toolchain driver side. On Wed, Nov 23, 2022 at 6:01 AM Palmer Dabbelt wrote: > > On Tue,

Re: Re: [PATCH] RISC-V: Bugfix for resolve_overloaded_builtin[PR113420]

you are right. vint8mf8_t test_vle8_v_i8mf8_m(vbool64_t vm, const int32_t *rs1, size_t vl) { return __riscv_vle8(vm, rs1, vl); } This will cause ICE. I tried clang and it will also cause ICE. xu...@eswincomputing.com From: juzhe.zh...@rivai.ai Date: 2024-01-19 15:53 To: Li Xu; gcc-patches

Re: Re: [PATCH] RISC-V: Bugfix for resolve_overloaded_builtin[PR113420]

Could you show me the ICE message ? Is it in front-end ? If yes, it's ok. I wonder whether it is "internal compiler error". juzhe.zh...@rivai.ai From: Li Xu Date: 2024-01-19 16:04 To: juzhe.zhong; gcc-patches CC: kito.cheng; palmer; zhengyu; pan2.li Subject: Re: Re: [PATCH] RISC-V: Bugfix fo

[PATCH] RISC-V: Fix RVV_VLMAX

This patch fixes memory hog found in SPEC2017 wrf benchmark which caused by RVV_VLMAX since RVV_VLMAX generate brand new rtx by gen_rtx_REG (Pmode, X0_REGNUM) every time we call RVV_VLMAX, that is, we are always generating garbage and redundant (reg:DI 0 zero) rtx. After this patch fix, the memo

Re: [PATCH] RISC-V: Fix RVV_VLMAX

LGTM, nice catch, I wasn't aware that would be a problem. On Fri, Jan 19, 2024 at 4:12 PM Juzhe-Zhong wrote: > > This patch fixes memory hog found in SPEC2017 wrf benchmark which caused by > RVV_VLMAX since RVV_VLMAX generate brand new rtx by gen_rtx_REG (Pmode, > X0_REGNUM) > every time we call

[PATCH V2] RISC-V: Fix RVV_VLMAX

This patch fixes memory hog found in SPEC2017 wrf benchmark which caused by RVV_VLMAX since RVV_VLMAX generate brand new rtx by gen_rtx_REG (Pmode, X0_REGNUM) every time we call RVV_VLMAX, that is, we are always generating garbage and redundant (reg:DI 0 zero) rtx. After this patch fix, the memo

Re: Re: [PATCH] RISC-V: Fix RVV_VLMAX

Thanks. I will commit V2 patch: https://gcc.gnu.org/pipermail/gcc-patches/2024-January/643420.html after I finishing testing. V2 no difference from V1 in codes except adding: PR target/113495 juzhe.zh...@rivai.ai From: Kito Cheng Date: 2024-01-19 16:19 To: Juzhe-Zhong CC: gcc-patches; kito.

[PATCH] sccvn: Don't use SCALAR_INT_TYPE_MODE on BLKmode BITINT_TYPEs [PR113459]

Hi! sccvn uses GET_MODE_SIZE (SCALAR_INT_TYPE_MODE (type)) for INTEGER_TYPEs, most likely because that is what native_{interpret,encode}_int used. This obviously doesn't work for larger BITINT_TYPEs which have BLKmode and the above ICEs on those. native_{interpret,encode}_int checks whether the B

[PATCH] gimple-ssa-warn-restrict: Only use type range from NOP_EXPR for non-narrowing conversions [PR113463]

Hi! builtin_memref::extend_offset_range when it sees a NOP_EXPR from INTEGRAL_TYPE (to INTEGRAL_TYPE of sizetype/ptrdifftype precision given the callers) uses wi::to_offset on TYPE_{MIN,MAX}_VALUE of the rhs1 type. This ICEs with large BITINT_TYPEs - to_offset is only supported for precisions up

Re: [PATCH v2 2/2] LoongArch: When the code model is extreme, the symbol address is obtained through macro instructions regardless of the value of -mexplicit-relocs.

在 2024/1/19 下午1:46, Xi Ruoyao 写道: On Wed, 2024-01-17 at 17:57 +0800, chenglulu wrote: Virtual register 1479 will be used in insn 2744, but register 1479 was assigned the REG_UNUSED attribute in the previous instruction. The attached file is the wrong file. The compilation command is as follow

Re: [PATCH v3] LoongArch: Define LOGICAL_OP_NON_SHORT_CIRCUIT

Hi, Jiahao: This patch will introduce redundant FAIL, and the reason needs to be explained. +FAIL: gcc.dg/tree-ssa/copy-headers-8.c scan-tree-dump-times ch2 "Conditional combines static and invariant" 1 +FAIL: gcc.dg/tree-ssa/copy-headers-8.c scan-tree-dump-times ch2 "Will duplicate bb" 2 +FAI

[PATCH] lower-bitint: Don't use m_loads for loads used in GIMPLE_ASM [PR113464]

Hi! Like for GIMPLE_PHIs or calls, even for GIMPLE_ASMs we want a corresponding VAR_DECL assigned for lhs SSA_NAMEs of loads from memory, as even GIMPLE_ASM relies on those VAR_DECLs to exist. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2024-01-19 Jakub Jelinek

Re: [PATCH] gimple-ssa-warn-restrict: Only use type range from NOP_EXPR for non-narrowing conversions [PR113463]

On Fri, 19 Jan 2024, Jakub Jelinek wrote: > Hi! > > builtin_memref::extend_offset_range when it sees a NOP_EXPR from > INTEGRAL_TYPE (to INTEGRAL_TYPE of sizetype/ptrdifftype precision > given the callers) uses wi::to_offset on TYPE_{MIN,MAX}_VALUE > of the rhs1 type. This ICEs with large BITINT

Re: [PATCH] sccvn: Don't use SCALAR_INT_TYPE_MODE on BLKmode BITINT_TYPEs [PR113459]

On Fri, 19 Jan 2024, Jakub Jelinek wrote: > Hi! > > sccvn uses GET_MODE_SIZE (SCALAR_INT_TYPE_MODE (type)) for INTEGER_TYPEs, > most likely because that is what native_{interpret,encode}_int used. > This obviously doesn't work for larger BITINT_TYPEs which have BLKmode > and the above ICEs on tho

Re: [PATCH] lower-bitint: Don't use m_loads for loads used in GIMPLE_ASM [PR113464]

On Fri, 19 Jan 2024, Jakub Jelinek wrote: > Hi! > > Like for GIMPLE_PHIs or calls, even for GIMPLE_ASMs we want > a corresponding VAR_DECL assigned for lhs SSA_NAMEs of loads > from memory, as even GIMPLE_ASM relies on those VAR_DECLs to exist. > > Bootstrapped/regtested on x86_64-linux and i686

[PATCH 1/3] rtl-ssa: Provide easier access to debug uses [PR113089]

This patch adds some accessors to set_info and use_info to make it easier to get at and iterate through uses in debug insns. It is used by the aarch64 load/store pair fusion pass in a subsequent patch to fix PR113089, i.e. to update debug uses in the pass. Bootstrapped/regtested as a series on aa

[PATCH 2/3] aarch64: Re-parent trailing nondebug base reg uses [PR113089]

While working on PR113089, I realised we where missing code to re-parent trailing nondebug uses of the base register in the case of cancelling writeback in the load/store pair pass. This patch fixes that. Bootstrapped/regtested as a series on aarch64-linux-gnu (with/without the pass enabled), OK

[PATCH 3/3] aarch64: Fix up debug uses in ldp/stp pass [PR113089]

As the PR shows, we were missing code to update debug uses in the load/store pair fusion pass. This patch fixes that. Note that this patch depends on the following patch to create new uses in RTL-SSA, submitted as part of the fixes for PR113070: https://gcc.gnu.org/pipermail/gcc-patches/2024-Janu

Re: [PATCH V2] RISC-V: Fix RVV_VLMAX

Ah, interesting that this was it. Thanks for fixing and also thanks to Andrew for suggesting that fix. Regards Robin

[PATCH] c++: Fix g++.dg/ext/attr-section2.C etc. with Solaris/SPARC as

The new g++.dg/ext/attr-section2*.C tests FAIL on Solaris/SPARC with the native assembler: +FAIL: g++.dg/ext/attr-section2.C -std=c++14 scan-assembler .(section|csect)[ t]+.foo +FAIL: g++.dg/ext/attr-section2.C -std=c++17 scan-assembler .(section|csect)[ t]+.foo +FAIL: g++.dg/ext/att

Re: HELP: Questions on unshare_expr

On Thu, Jan 18, 2024 at 3:46 PM Qing Zhao wrote: > > > > > On Jan 17, 2024, at 1:43 AM, Richard Biener > > wrote: > > > > On Wed, Jan 17, 2024 at 7:42 AM Richard Biener > > wrote: > >> > >> On Tue, Jan 16, 2024 at 9:26 PM Qing Zhao wrote: > >>> > >>> > >>> > On Jan 15, 2024, at 4:31 AM, R

[PATCH 0/5] RISC-V: Relax the -march string for accept any order

Hi, kito. I found these following regression: FAIL: gcc.target/riscv/arch-27.c -O0 at line 7 (test for errors, line ) FAIL: gcc.target/riscv/arch-27.c -O0 (test for excess errors) FAIL: gcc.target/riscv/arch-27.c -O1 at line 7 (test for errors, line ) FAIL: gcc.target/riscv/arch-27.c

Re: [PATCH 0/5] RISC-V: Relax the -march string for accept any order

Oh, ok, I must have missed something during testing. On Fri, Jan 19, 2024 at 5:37 PM juzhe.zh...@rivai.ai wrote: > > Hi, kito. > > I found these following regression: > > FAIL: gcc.target/riscv/arch-27.c -O0 at line 7 (test for errors, line ) > FAIL: gcc.target/riscv/arch-27.c -O0 (test fo

[PATCH v2] RISC-V: Documnet the list of supported extensions

Try to list all supported extensions: name, version and few description for each extension. v2 changes: - Fix several typo. - Add expantion info for vector crypto extensions. - Drop zvl8192b, zvl16384b, zvl32768b and zvl65536b. - Aadd zicntr and zihpm gcc/ChangeLog: * doc/invoke.texi

Re: [PATCH v2] RISC-V: Documnet the list of supported extensions

LGTM. juzhe.zh...@rivai.ai From: Kito Cheng Date: 2024-01-19 17:40 To: gcc-patches; kito.cheng; jim.wilson.gcc; palmer; andrew; jeffreyalaw; christoph.muellner; juzhe.zhong; rep.dot.nop CC: Kito Cheng Subject: [PATCH v2] RISC-V: Documnet the list of supported extensions Try to list all suppor

Re: [PATCH] RISC-V: Tweak the wording for the sorry message

On 19 January 2024 03:41:57 CET, Kito Cheng wrote: >Thanks, pushed to trunk :) Thanks, but don't you have to update the tests too, at least gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c ? thanks > >On Fri, Jan 19, 2024 at 10:36 AM juzhe.zh...@rivai.ai > wrote: >> >> OK >> >> __

[PATCH] tree-optimization/113494 - Fix two observed regressions with r14-8206

The following handles the situation where we lack a loop-closed PHI for a virtual operand because a loop exit goes to a code region not having any virtual use (an endless loop). It also handles the situation of edge redirection re-allocating a PHI node in the destination block so we have to re-loo

Re: [PATCH] RISC-V: Documnet the list of supported extensions

Hi Bernhard: Thanks for such careful review! V2 send :) On Tue, Jan 16, 2024 at 4:08 AM Bernhard Reutner-Fischer wrote: > > Hi Kito! > > On Thu, 11 Jan 2024 17:06:09 +0800 > Kito Cheng wrote: > > > Try to list all supported extensions: name, version and few description > > for each extension. >

Re: Re: [PATCH] RISC-V: Tweak the wording for the sorry message

Yeah. There is regression here: Executing on host: /work/home/jzzhong/work/docker/riscv-gnu-toolchain/build/dev-rv64gcv-lp64d-medany-newlib-spike-release-m1-scalable/build-gcc-newlib-stage2/gcc/xgcc -B/work/home/jzzhong/work/docker/riscv-gnu-toolchain/build/dev-rv64gcv-lp64d-medany-newlib-spike

[PATCH] debug/113488 - DW_AT_abstract_origin to self

The new sanity check avoiding creating of DIE refs to self triggers on the PRs testcase when using -g1 and -ffat-lto-objects as while early DWARF with -g1 doesn't contain any DIEs for LABEL_DECLs later cloning will still mark DECLs as in if they would via dwarf2out_abstract_function calling set_blo

Re: [PATCH v3] LoongArch: Define LOGICAL_OP_NON_SHORT_CIRCUIT

The test case gcc.dg/tree-ssa/copy-headers-8.c fails for a target where LOGICAL_OP_NON_SHORT_CIRCUIT is defined as 0.It is suggested to add `--param logical-op-non-short-circuit=1` to the test case to make it a target-independent testcase. see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=11124

Re: [PATCH] libgomp: Fix build for -fshort-enums

On 11.09.23 14:57, Sebastian Huber wrote: On 04.07.23 08:20, Sebastian Huber wrote: On 22.05.23 14:51, Sebastian Huber wrote: Make sure that the API enums have at least the size of int. Otherwise the following build error may occur: In file included from gcc/libgomp/env.c:34: ./libgomp_f.h:

Re: [PATCH v2] RISC-V: Documnet the list of supported extensions

Pushed to trunk, thanks :) On Fri, Jan 19, 2024 at 5:41 PM juzhe.zh...@rivai.ai wrote: > > LGTM. > > > juzhe.zh...@rivai.ai > > > From: Kito Cheng > Date: 2024-01-19 17:40 > To: gcc-patches; kito.cheng; jim.wilson.gcc; palmer; andrew; jeffreyalaw; > christoph.mue

[committed] RISC-V: Update testcase due to message update

gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-27.c: Update scan message. * gcc.target/riscv/arch-28.c: Ditto. * gcc.target/riscv/attribute-10.c: Ditto. * gcc.target/riscv/rvv/base/big_endian-2.c: Ditto. * gcc.target/riscv/rvv/base/zvl-unimplemented-1.c: D

Re: [committed] RISC-V: Update testcase due to message update

Ok. juzhe.zh...@rivai.ai From: Kito Cheng Date: 2024-01-19 18:08 To: rep.dot.nop; jeffreyalaw; rdapp.gcc; juzhe.zhong; gcc-patches CC: Kito Cheng Subject: [committed] RISC-V: Update testcase due to message update gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-27.c: Update scan message. * g

[PATCH] MIPS: Accept arguments for -mexplicit-relocs

GAS introduced explicit relocs since 2001, and %pcrel_hi/low were introduced in 2014. In future, we may introduce more. Let's convert -mexplicit-relocs option, and accpet options: none, base, pcrel. We also update gcc/configure.ac to set the value to option the gas support when GCC itself is

Re: [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of multi-word shifts/rotates.

On Thu, Jan 18, 2024 at 8:55 PM Roger Sayle wrote: > > > This patch tweaks RTL expansion of multi-word shifts and rotates to use > PLUS rather than IOR for disjunctive operations. During expansion of > these operations, the middle-end creates RTL like (X<>C2) > where the constants C1 and C2 guara

Re: [PATCH] libgccjit: Add ability to get CPU features

David: Ping. On Thu, 2023-11-09 at 18:04 -0500, David Malcolm wrote: > On Thu, 2023-11-09 at 17:27 -0500, Antoni Boucher wrote: > > Hi. > > This patch adds support for getting the CPU features in libgccjit > > (bug > > 112466) > > > > There's a TODO in the test: > > I'm not sure how to test that

RE: [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of multi-word shifts/rotates.

Hi Richard, Thanks for the speedy review. I completely agree this patch can wait for stage1, but it's related to some recent work Andrew Pinski has been doing in match.pd, so I thought I'd share it. Hypothetically, recognizing (x<<4)+(x>>60) as a rotation at the tree-level might lead to a code

Re: [PATCH] testsuite: Disable test for PR113292 on targets without TLS support

On Fri, 19 Jan 2024 at 08:41, Nathaniel Shead wrote: > > Tested on x86_64-pc-linux-gnu using a cross-compiler to > arm-unknown-linux-gnueabihf with --enable-threads=0 that the link test > is correctly skipped. OK for trunk? > > -- >8 -- > > This disables the new test added by r14-8168 on machines

Re: [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of multi-word shifts/rotates.

On Fri, Jan 19, 2024 at 2:26 PM Roger Sayle wrote: > > > Hi Richard, > > Thanks for the speedy review. I completely agree this patch > can wait for stage1, but it's related to some recent work Andrew > Pinski has been doing in match.pd, so I thought I'd share it. > > Hypothetically, recognizing (

[PATCHSET] Update of GCC upstream with gccrs development repository

Hi everyone, This patchset updates trunk with all of 2023's commits concerning the Rust GCC frontend. We apologize for the large amount of changes - we will change our upstreaming process for 2024 and will update upstream on a more regular basis. This patchset contains multiple improvement

[PATCH] tree-optimization/113373 - add missing LC PHIs for live operations

The following makes reduction epilogue code generation happy by properly adding LC PHIs to the exit blocks for multiple exit vectorized loops. Some refactoring might make the flow easier to follow but I've refrained from doing that with this patch. I've kept some fixes in reduction epilogue gener

[PATCH] aarch64: Don't assert recog success in ldp/stp pass [PR113114]

Hi, The PR shows two different cases where try_promote_writeback produces an RTL pattern which isn't recognized. Currently this leads to an ICE, as we assert recog success, but I think it's better just to back out of the changes gracefully if recog fails (as we do in the main fuse_pair case). In

[PATCH v3 0/2] arm: Add support for MVE Tail-Predicated Low Overhead Loops

Hi, Reworked the patches according to Kyrill's comments, made some other non-functional changes and rebased. Reposting as v3 so patchworks picks them up and runs the necessary testing. Andre Vieira (2): arm: Add define_attr to to create a mapping between MVE predicated and unpredicated insns a

[PATCH v3 2/2] arm: Add support for MVE Tail-Predicated Low Overhead Loops

Respin after comments from Kyrill and rebase. I also removed an if-then-else construct in arm_mve_check_reg_origin_is_num_elems similar to the other functions Kyrill pointed out. After an earlier comment from Richard Sandiford I also added comments to the two tail predication patterns added to e

[PATCH v3 1/2] arm: Add define_attr to to create a mapping between MVE predicated and unpredicated insns

Reposting for testing purposes, no changes from v2 (other than rebase). diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 2a2207c0ba1..449e6935b32 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2375,6 +2375,21 @@ extern int making_const_table; else if (TARGET_THUM

[PATCH] libstdc++: Add and to stdc++.h

Tested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- libstdc++-v3/ChangeLog: * include/precompiled/stdc++.h [_GLIBCXX_HOSTED]: Include and for C++23 and C++26 respectively. --- libstdc++-v3/include/precompiled/stdc++.h | 5 + 1 file changed, 5 insertions(+)

Re: [PATCH] libstdc++: Add and to stdc++.h

On Fri, 19 Jan 2024 at 15:16, Patrick Palka wrote: > > Tested on x86_64-pc-linux-gnu, does this look OK for trunk? OK. This was on my TODO list after somebody asked about on IRC this week, so thanks for doing it. > > -- >8 -- > > libstdc++-v3/ChangeLog: > > * include/precompiled/stdc+

Re: [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of multi-word shifts/rotates.

Am 18.01.24 um 20:54 schrieb Roger Sayle: This patch tweaks RTL expansion of multi-word shifts and rotates to use PLUS rather than IOR for disjunctive operations. During expansion of these operations, the middle-end creates RTL like (X<>C2) where the constants C1 and C2 guarantee that bits d

[committed] Skip gcc.dg/analyzer/pr94688.c on hppa*64*-*-*

Tested on hppa64-hp-hpux11.11. Committed to trunk. Dave --- Skip gcc.dg/analyzer/pr94688.c on hppa*64*-*-* 2024-01-19 John David Anglin gcc/testsuite/ChangeLog: PR analyzer/112705 * gcc.dg/analyzer/pr94688.c: Skip on hppa*64*-*-*. diff --git a/gcc/testsuite/gcc.dg/analyzer

[committed] Only xfail gcc.dg/pr84877.c on 32-bit hppa*-*-*

Tested on hppa64-hp-hpux11.11. Committed to trunk. Dave --- Only xfail gcc.dg/pr84877.c on 32-bit hppa*-*-* 2024-01-19 John David Anglin gcc/testsuite/ChangeLog: * gcc.dg/pr84877.c: Only xfail on 32-bit hppa*-*-*. diff --git a/gcc/testsuite/gcc.dg/pr84877.c b/gcc/testsuite/gcc.dg/

Re: HELP: Questions on unshare_expr

> On Jan 19, 2024, at 4:30 AM, Richard Biener > wrote: > > On Thu, Jan 18, 2024 at 3:46 PM Qing Zhao wrote: >> >> >> >>> On Jan 17, 2024, at 1:43 AM, Richard Biener >>> wrote: >>> >>> On Wed, Jan 17, 2024 at 7:42 AM Richard Biener >>> wrote: On Tue, Jan 16, 2024 at 9:26 PM Q

Re: [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of multi-word shifts/rotates.

On 1/19/24 09:05, Georg-Johann Lay wrote: Am 18.01.24 um 20:54 schrieb Roger Sayle: This patch tweaks RTL expansion of multi-word shifts and rotates to use PLUS rather than IOR for disjunctive operations.  During expansion of these operations, the middle-end creates RTL like (X<>C2) where

[committed] Change dg-options for hpux to define _HPUX_SOURCE in gcc.dg/pthread-init-2.c

Tested on hppa64-hp-hpux11.11. Committed to trunk. Dave --- Change dg-options for hpux to define _HPUX_SOURCE in gcc.dg/pthread-init-2.c Pthreads on hpux needs _HPUX_SOURCE define for id_t and spu_t types. 2024-01-19 John David Anglin gcc/testsuite/ChangeLog: * gcc.dg/pthread-init

[committed] Limit dg-xfail-run-if for *-*-hpux11.[012]* to -O0

Tested on hppa64-hp-hpux11.11. Committed to trunk. Dave --- Limit dg-xfail-run-if for *-*-hpux11.[012]* to -O0 2024-01-19 John David Anglin gcc/testsuite/ChangeLog: * gcc.dg/torture/pr47917.c: Limit dg-xfail-run-if for hpux11.[012]* to -O0. diff --git a/gcc/testsuite/gcc.d

[PATCH] fortran: Restore current interface info on error [PR111291]

Hello, I tested this on x86_64-pc-linux-gnu without regression. There is no new test, as the problem is visible on an existing test with valgrind or an asan-instrumented compiler. OK for master? -- >8 -- This change is a followup to the fix for PR48776 (namely r14-3572-gd58150452976c4ca65ddc811

Re: [PATCH] RISC-V: Add split pattern to generate SFB instructions. [PR113095]

On 1/19/24 00:09, Kito Cheng wrote: Thanks! generally LGTM, but I would wait one more week to see any other comments :)Just a note. 113095 isn't marked as a regression, but it most definitely is a regression. So this meets the stage4 criteria. On Fri, Jan 19, 2024 at 3:05 PM Monk Chian

[Patch] xfail libgomp.c/declare-variant-4-{fiji,gfx803}.c

The problem is as described at https://gcc.gnu.org/install/specific.html#amdgcn-x-amdhsa "Note that support for Fiji devices has been removed in ROCm 4.0 and support in LLVM is deprecated and will be removed in LLVM 18." Therefore, GCC is no longer build with Fiji (gfx803) support by default

[pushed] c++: alias template argument conversion [PR112632]

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- We've had a problem with lost conversions to template parameter types for a while now; looking at this PR, it occurred to me that the problem is really with alias (and concept) templates, since we do substitution of dependent arguments into

Ping [PATCH 1/6] Add -mcpu=future

Ping | Date: Fri, 5 Jan 2024 18:35:37 -0500 | From: Michael Meissner | Subject: Repost [PATCH 1/6] Add -mcpu=future | Message-ID: https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641961.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.co

Ping [PATCH 2/6] PowerPC: Make -mcpu=future enable -mblock-ops-vector-pair.

Ping | Date: Fri, 5 Jan 2024 18:37:17 -0500 | From: Michael Meissner | Subject: Repost [PATCH 2/6] PowerPC: Make -mcpu=future enable -mblock-ops-vector-pair. | Message-ID: https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641962.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachuset

Ping [PATCH 3/6] PowerPC: Add support for accumulators in DMR registers.

Ping | Date: Fri, 5 Jan 2024 18:38:23 -0500 | From: Michael Meissner | Subject: Repost [PATCH 3/6] PowerPC: Add support for accumulators in DMR registers. | Message-ID: https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641963.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts,

Ping [PATCH 4/6] PowerPC: Make MMA insns support DMR registers.

Ping | Date: Fri, 5 Jan 2024 18:39:55 -0500 | From: Michael Meissner | Subject: Repost [PATCH 4/6] PowerPC: Make MMA insns support DMR registers. | Message-ID: https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641964.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 0143

Ping [PATCH 5/6] PowerPC: Switch to dense math names for all MMA operations.

Ping | Date: Fri, 5 Jan 2024 18:40:58 -0500 | From: Michael Meissner | Subject: Repost [PATCH 5/6] PowerPC: Switch to dense math names for all MMA operations. | Message-ID: https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641965.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachuse

Ping [PATCH 6/6] PowerPC: Add support for 1,024 bit DMR registers.

Ping | Date: Fri, 5 Jan 2024 18:42:02 -0500 | From: Michael Meissner | Subject: Repost [PATCH 6/6] PowerPC: Add support for 1,024 bit DMR registers. | Message-ID: https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641966.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 0

Ping [PATCH, V2] PR target/112886, Add %S to print_operand for vector pair support.

Ping | Date: Thu, 11 Jan 2024 12:29:23 -0500 | From: Michael Meissner | Subject: [PATCH, V2] PR target/112886, Add %S to print_operand for vector pair support. | Message-ID: https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642727.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachus

Re: c++/modules: Emit definitions of ODR-used static members imported from modules [PR112899]

On Wed, 3 Jan 2024, Nathaniel Shead wrote: > Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk? > > -- >8 -- > > Static data members marked 'inline' should be emitted in TUs where they > are ODR-used. We need to make sure that statics imported from modules > are correctly added to

Re: [PATCH] fortran: Restore current interface info on error [PR111291]

On Fri, Jan 19, 2024 at 06:47:36PM +0100, Mikael Morin wrote: > > I tested this on x86_64-pc-linux-gnu without regression. > There is no new test, as the problem is visible on an > existing test with valgrind or an asan-instrumented compiler. > OK for master? > Yes. After your explanation, the

Re: [PATCH 1/2] RISC-V: delete all the vector psabi checking.

../../gcc/config/riscv/riscv.cc: In function 'void riscv_init_cumulative_args(CUMULATIVE_ARGS*, tree, rtx, tree, int)': ../../gcc/config/riscv/riscv.cc:4879:34: error: unused parameter 'fndecl' [-Werror=unused-parameter] 4879 | tree fndecl, |

[committed] libstdc++: Fix P2255R2 dangling checks for std::tuple in C++17 [PR108822]

Tested powerp64le-linux. Pushed to trunk. -- >8 -- I accidentally used && in a fold-expression instead of || which meant that in C++17 the tuple(UElements&&...) constructor only failed its debug assertion if all tuple elements were dangling references. Some missing tests (noted as "TODO") meant t

[committed] libstdc++: Do not use CTAD for _Utf32_view alias template (redux)

Tested powerp64le-linux. Pushed to trunk. -- >8 -- My change in r14-8181-g665a3ff1539ce2 was incomplete as there's a second place using CTAD with the _Utf32_view alias template. This fixes it. libstdc++-v3/ChangeLog: * include/std/format (_Spec::_M_parse_fill_and_align): Do not

[pushed] c++: requires and using-decl [PR113498]

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- get_template_info was crashing because it assumed that any decl with DECL_LANG_SPECIFIC could use DECL_TEMPLATE_INFO. It's more complicated than that. PR c++/113498 gcc/cp/ChangeLog: * pt.cc (decl_template_info): New fn.

Re: [PATCH v5] RISC-V: Support XTheadVector extension

On 1/18/24 07:43, Christoph Müllner wrote: On Fri, Jan 12, 2024 at 4:18 AM Jun Sha (Joshua) wrote: This patch series presents gcc implementation of the XTheadVector extension [1]. [1] https://github.com/T-head-Semi/thead-extension-spec/ For some vector patterns that cannot be avoided, we

[patch][gcn] mkoffload: Fix linking with "-g"; fix file deletion; improve diagnostic [PR111966]

This patch fixes PR111966, i.e. when compiling offloaded code with "-g" but without "-march=", mkoffload created a file with e_flags set to gfx803/fiji as architecture - while all other files used gfx900, which the linker did not like. Reason: When the default was changed, this flag was missed

Re: [PATCH] libgccjit: Add vector permutation and vector access operations

David: Ping. On Thu, 2023-11-30 at 17:16 -0500, Antoni Boucher wrote: > All of these are fixed in this new patch. > Thanks for the review. > > On Mon, 2023-11-20 at 18:05 -0500, David Malcolm wrote: > > On Fri, 2023-11-17 at 17:36 -0500, Antoni Boucher wrote: > > > Hi. > > > This patch adds a vec

[PATCH, committed] Fortran: fix wrong array bounds check [PR113471]

Dear all, I've pushed the attached obvious patch for a regression due to a wrong array bounds check after regtesting on x86_64-pc-linux-gnu and verification of the fix by the reporter in the PR. https://gcc.gnu.org/g:94b2e6cb1cc4feb122bf77f19a657c97bffa9b42 Thanks, Harald From 94b2e6cb1cc4feb12

Re: [PATCH] libgccjit: Allow comparing aligned int types

David: Ping. On Thu, 2023-12-21 at 08:33 -0500, Antoni Boucher wrote: > Hi. > This patch allows comparing aligned integer types as equal. > There's a TODO in the code about whether we should check that the > alignment is equal. > What are your thoughts on this? > > Thanks for the review.

Re: [PATCH] libgccjit: Allow sending a const pointer as argument

David: Ping. On Thu, 2023-12-21 at 11:59 -0500, Antoni Boucher wrote: > Hi. > This patch adds the ability to send const pointer as argument to a > function. > Thanks for the review.

Re: [PATCH] libgccjit: Add convert vector

David: Ping. On Thu, 2023-12-21 at 16:01 -0500, Antoni Boucher wrote: > Hi. > This patch adds the support for the convert vector internal function. > I'll need to double-check that making the decl a register is > necessary. > Thanks for the review.

Re: [committed] Fix comment typos

Hi Just another commentary typo.. On 17 January 2024 11:23:01 CET, Jakub Jelinek wrote: >--- gcc/gengtype.cc.jj 2024-01-03 11:51:23.314845233 +0100 >+++ gcc/gengtype.cc2024-01-16 18:56:57.383009291 +0100 >@@ -4718,8 +4718,8 @@ write_roots (pair_p variables, bool emit > } > > /* Prints not-

Re: Fix merging of value predictors

On 17 January 2024 14:20:49 CET, Jan Hubicka wrote: >--- a/gcc/predict.def >+++ b/gcc/predict.def >@@ -94,6 +94,16 @@ DEF_PREDICTOR (PRED_LOOP_ITERATIONS_GUESSED, "guessed loop >iterations", > DEF_PREDICTOR (PRED_LOOP_ITERATIONS_MAX, "guessed loop iterations", > PROB_UNINITIALIZED,

Re: [PATCH] modula2: Many powerpc platforms do _not_ have support for IEEE754 long double [PR111956]

Richard Biener writes: > On Thu, Jan 18, 2024 at 1:58 AM Gaius Mulley wrote: >> >> >> ok for master ? >> >> Bootstrapped on power8 (cfarm135), power9 (cfarm120) and >> x86_64-linux-gnu. > > OK. many thanks! > I wonder what this does to the libm2 ABI? ah yes - I'll open a PR reflecting lack of

[PATCH] libgccjit: Add support for creating temporary variables

Hi. This patch adds a new way to create local variable that won't generate debug info: it is to be used for compiler-generated variables. Thanks for the review. From 6f69e9db77f3c7e019fae74414ba5eed15298514 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Thu, 18 Jan 2024 16:54:59 -0500 Subject

[PATCH] libgccjit: Allow comparing array types

Hi. This patch allows comparing different instances of array types as equal. Thanks for the review. From ef4afd9de440f10502f3cc84b2112cf83cde2610 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Tue, 2 Jan 2024 16:04:10 -0500 Subject: [PATCH] libgccjit: Allow comparing array types gcc/jit/Chan

[PATCH] libgccjit: Add gcc_jit_global_set_readonly

Hi. This patch adds a new API gcc_jit_global_set_readonly: it's equivalent to having a const global variable, but it is useful in the case of complex compilers where it is not convenient to use const. Thanks for the review. From ff3aa19207a6cdaeff6fcb6521ad2ad92f5448ff Mon Sep 17 00:00:00 2001 From

Re: [PATCH, V2] PR target/112886, Add %S to print_operand for vector pair support.

On 1/11/24 11:29 AM, Michael Meissner wrote: > This is version 2 of the patch. The only difference is I made the test case > simpler to read. [snip] > gcc/ > > PR target/112886 > * config/rs6000/rs6000.cc (print_operand): Add %S output modifier. > * doc/md.texi (Modifiers): Ment

[PATCH] c++/modules: Handle partial specialisations in GMF [PR113405]

Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk? -- >8 -- Currently, when exporting names from the GMF, or within header modules, for a set of constrained partial specialisations we only emit the first one. This is because the 'type_specialization' list only includes a single spec

Re: [PATCH] Avoid ICE in single-bit logical RMWs on m68k-uclinux [PR108640]

On 1/18/24 09:39, Mikael Pettersson wrote: When generating RMW logical operations on m68k, the backend recognizes single-bit operations and rewrites them as bit instructions on operands adjusted to address the intended byte. When offsetting the addresses the backend keeps the modes as SImode,

Re: [PATCH] Avoid ICE on m68k -fzero-call-used-regs -fpic [PR110934]

On 1/17/24 10:03, Mikael Pettersson wrote: PR110934 is a problem on m68k where -fzero-call-used-regs -fpic ICEs when clearing an FP register. The generic code generates an XFmode move of zero to that register, which becomes an XFmode load from initialized data, which due to -fpic uses a non-c

[Committed] RISC-V: Suppress warning

../../gcc/config/riscv/riscv.cc: In function 'void riscv_init_cumulative_args(CUMULATIVE_ARGS*, tree, rtx, tree, int)': ../../gcc/config/riscv/riscv.cc:4879:34: error: unused parameter 'fndecl' [-Werror=unused-parameter] 4879 | tree fndecl, |

Re: [Committed] RISC-V: Suppress warning

On 1/19/24 17:27, Juzhe-Zhong wrote: ../../gcc/config/riscv/riscv.cc: In function 'void riscv_init_cumulative_args(CUMULATIVE_ARGS*, tree, rtx, tree, int)': ../../gcc/config/riscv/riscv.cc:4879:34: error: unused parameter 'fndecl' [-Werror=unused-parameter] 4879 |

Re: Re: [Committed] RISC-V: Suppress warning

OK. I saw the other arguments there: tree fntype ATTRIBUTE_UNUSED, rtx libname ATTRIBUTE_UNUSED, So I leverage these and add ATTRIBUTE_UNUSED to 'fndecl' Maybe it's better remove all arguments for riscv_init_cumulative_args which are unuse

[PATCH] libstdc++: suppress -Wdangling-reference with operator| [PR111410]

Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? -- >8 -- It seems to me that we should exclude std::ranges::views::__adaptor::operator| from the -Wdangling-reference warning. It's commonly used when handling ranges. PR c++/111410 libstdc++-v3/ChangeLog: * include/s

[PATCH] c++: -Wdangling-reference and lambda false warning [PR109640]

Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? -- >8 -- -Wdangling-reference checks if a function receives a temporary as its argument, and only warns if any of the arguments was a temporary. But we should not warn when the temporary represents a lambda or we generate false positive

Re: [PATCH] libstdc++: suppress -Wdangling-reference with operator| [PR111410]

On Sat, 20 Jan 2024, 03:47 Marek Polacek, wrote: > Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk? > OK, thanks. The standard ranges have their own protection against dangling via the opt-in borrowed_range concept, and algorithms that don't allow returning iterators into rvalue ran