Re: Re: [PATCH v4 2/3] RISC-V: Add crypto machine descriptions

2023-12-20 15:12 juzhe.zhong wrote: >+   (and:VI >+ (match_operand:VI 3 "register_operand" "vr, vr, vr, vr") >+ (not:VI (match_operand:VI 4 "register_operand" "vr, vr, vr, vr"))) >Swap the order: > >(not:VI (match_operand:VI 4 "register_operand" "vr, vr, vr, vr") >

Re: Re: [PATCH v4 2/3] RISC-V: Add crypto machine descriptions

>> The description in the spec is"Each bit of Op1 is inverted and logically >> ANDed with the corresponding bits in vs2", >> so I think the "and" should be placed outside. Ah. Yes. juzhe.zh...@rivai.ai From: Feng Wang Date: 2023-12-20 16:09 To: juzhe.zh...@rivai.ai; gcc-patches CC: kito.chen

[PATCH] RISC-V: Fix calculation of max live vregs

For the stmt _1 = _2 + _3, assume that _2 or _3 not used after this stmt. _1 can use same register with _2 or _3 if without early clobber. Two registers are needed, but current calculation is three. This patch preserves point 0 for bb entry and excludes its def when calculates live regs of certain

[PATCH FYI] www: new AdaCore-contributed hardening features in gcc 13 and 14

On Nov 30, 2023, Richard Biener wrote: >> >> Here are changes.html entries for this and for the other newly-added >> >> features: >> >> > LGTM. (sorry, I should be following up two messages upthread, but I don't seem to have saved that one) I've finally put in the www changes. Mention harden

[Committed] RISC-V: Fix ICE of moving SUBREG of vector mode to DImode scalar register on RV32 system.

This patch fixes following ICE on full coverage testing of RV32. Running target riscv-sim/-march=rv32gc_zve32f/-mabi=ilp32d/-mcmodel=medlow/--param=riscv-autovec-lmul=dynamic FAIL: gcc.c-torture/compile/930120-1.c -O2 (internal compiler error: in emit_move_insn, at expr.cc:4606) FAIL: gcc.c-t

[PATCH] RISC-V: Fix RISCV_FUSE_ZEXTWS fusion condition

From: wangpc The condition is RISCV_FUSE_ZEXTH, which is a mistake. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix condition. --- gcc/config/riscv/riscv.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/ris

[Patchv3, rs6000] Correct definition of macro of fixed point efficient unaligned

Hi, The patch corrects the definition of TARGET_EFFICIENT_OVERLAPPING_UNALIGNED and replace it with the call of slow_unaligned_access. Compared with last version, https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640832.html the main change is to pass alignment measured by bits to slow_u

[Patch, rs6000] Call library for block memory compare when optimizing for size

Hi, This patch call library function for block memory compare when it's optimized for size. Bootstrapped and tested on x86 and powerpc64-linux BE and LE with no regressions. Is this OK for trunk? Thanks Gui Haochen ChangeLog rs6000: Call library for block memory compare when optimizing for s

[PATCH] sched: Don't skip empty block by removing no_real_insns_p [PR108273]

Hi, This patch follows Richi's suggestion "scheduling shouldn't special case empty blocks as they usually do not appear" in [1], it removes function no_real_insns_p and its uses completely. There is some case that one block previously has only one INSN_P, but while scheduling some other blocks th

[PATCH v2] aarch64: Validate register operands early in ldp fusion pass [PR113062]

This is a v2 addressing Richard's feedback, v1 was posted here: https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640957.html Bootstrapped/regtested on aarch64-linux-gnu, OK for trunk? Thanks, Alex -- >8 -- We were missing validation of the candidate register operands in the ldp/stp pass.

Re: [PATCH] fold-const: Handle AND, IOR, XOR with stepped vectors [PR112971].

Richard Biener writes: > On Tue, 19 Dec 2023, Andrew Pinski wrote: > >> On Tue, Dec 19, 2023 at 2:40?AM Richard Sandiford >> wrote: >> > >> > Richard Biener writes: >> > > On Tue, 19 Dec 2023, juzhe.zh...@rivai.ai wrote: >> > > >> > >> Hi, Richard. >> > >> >> > >> After investigating the codes:

Re: [PATCH v2] aarch64: Validate register operands early in ldp fusion pass [PR113062]

Alex Coplan writes: > This is a v2 addressing Richard's feedback, v1 was posted here: > https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640957.html > > Bootstrapped/regtested on aarch64-linux-gnu, OK for trunk? > > Thanks, > Alex > > -- >8 -- > > We were missing validation of the candidate

[PATCH v3] RISC-V: Bugfix for the const vector in single steps

From: Pan Li This patch would like to fix the below execution failure when build with "-march=rv64gcv_zvl512b -mabi=lp64d -mcmodel=medlow --param=riscv-autovec-lmul=m8 -ftree-vectorize -fno-vect-cost-model -O3" FAIL: gcc.dg/vect/pr92420.c -flto -ffat-lto-objects execution test The will be one

Re: [PATCH v3] RISC-V: Bugfix for the const vector in single steps

OK。 juzhe.zh...@rivai.ai From: pan2.li Date: 2023-12-20 17:35 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng; jeffreyalaw Subject: [PATCH v3] RISC-V: Bugfix for the const vector in single steps From: Pan Li This patch would like to fix the below execution failure when b

Re: [PATCH v2 1/3] RISC-V: movmem for RISCV with V extension

Hi, this patchset has been tested with the following configurations: rv64gcv_zvl128b rv64gcv_zvl256b rv32imafd_zve32x1p0 rv32gc_zve64f_zvl128b Will fix the formatting in v3. Thanks On Wed, Dec 20, 2023 at 5:28 AM Jeff Law wrote: > > > On 12/19/23 02:53, Sergei Lewis wrote: > > gcc/ChangeLog

Re: [PATCH v2 2/3] RISC-V: setmem for RISCV with V extension

Hi, This has been tested with the following configurations: rv64gcv_zvl128b rv64gcv_zvl256b rv32imafd_zve32x1p0 rv32gc_zve64f_zvl128b I'll drop the constraints and add the testing info to the cover email in v3. I'll hold off submitting v3 until gcc-15 as requested. On Wed, Dec 20, 2023 at 5:38 A

Re: [PATCH] tree-optimization/113073 - amend PR112736 fix

Hi! On 2023-12-19T13:30:58+0100, Richard Biener wrote: > The PR112736 testcase fails on RISC-V because the aligned exception > uses the wrong check. The alignment support scheme can be > dr_aligned even when the access isn't aligned to the vector size > but some targets are happy with element al

Re: [PATCH] RISC-V: Fix calculation of max live vregs

Hi, Han. It's awesome that some one want to optimize dynamic LMUL feature of GCC. I knew this feature is not stable yet and I failed to find the time to optimize it (Still busy with fixing bugs). Could you give me more details why this patch can refine those 2 cases with picking larger LMUL (I

Re: [PATCH] fold-const: Handle AND, IOR, XOR with stepped vectors [PR112971].

On Wed, 20 Dec 2023, Richard Sandiford wrote: > Richard Biener writes: > > On Tue, 19 Dec 2023, Andrew Pinski wrote: > > > >> On Tue, Dec 19, 2023 at 2:40?AM Richard Sandiford > >> wrote: > >> > > >> > Richard Biener writes: > >> > > On Tue, 19 Dec 2023, juzhe.zh...@rivai.ai wrote: > >> > > > >

[PATCH] lower-bitint: Fix up handling of nested casts in mergeable stmt handling [PR112941]

Hi! The following patch fixes 2 issues in handling of casts for mergeable stmts. The first hunk fixes the case when we have two nested casts (typically after optimization that is zero-extension of a sign-extension because everything else should have been folded into a single cast). If the lowerin

Re: [PATCH] tree-optimization/113073 - amend PR112736 fix

On Wed, 20 Dec 2023, Thomas Schwinge wrote: > Hi! > > On 2023-12-19T13:30:58+0100, Richard Biener wrote: > > The PR112736 testcase fails on RISC-V because the aligned exception > > uses the wrong check. The alignment support scheme can be > > dr_aligned even when the access isn't aligned to the

Re: [PATCH] lower-bitint: Fix up handling of nested casts in mergeable stmt handling [PR112941]

On Wed, 20 Dec 2023, Jakub Jelinek wrote: > Hi! > > The following patch fixes 2 issues in handling of casts for mergeable > stmts. > The first hunk fixes the case when we have two nested casts (typically > after optimization that is zero-extension of a sign-extension because > everything else sho

Re: [PATCH 5/5] OpenMP: Add prettyprinter support for context selectors.

On 17.12.23 20:03, Sandra Loosemore wrote: With the change to use enumerators instead of strings to represent context selector and selector-set names, the default tree-list output for dumping selectors is less helpful for debugging and harder to use in test cases. This patch adds support for dum

Patch ping (Re: [PATCH] i386: Make most MD builtins nothrow, leaf [PR112962])

Hi! On Wed, Dec 13, 2023 at 10:21:43AM +0100, Jakub Jelinek wrote: > The following patch makes most of x86 MD builtins nothrow,leaf > (like most middle-end builtins are). For -fnon-call-exceptions it > doesn't nothrow, better might be to still add it if the builtins > don't read or write memory a

Re: [PATCH] i386: Make most MD builtins nothrow, leaf [PR112962]

On Wed, Dec 13, 2023 at 10:21 AM Jakub Jelinek wrote: > > Hi! > > The following patch makes most of x86 MD builtins nothrow,leaf > (like most middle-end builtins are). For -fnon-call-exceptions it > doesn't nothrow, better might be to still add it if the builtins > don't read or write memory and

RE: [PATCH 3/21]middle-end: Implement code motion and dependency analysis for early breaks

> > + /* If we've moved a VDEF, extract the defining MEM and update > > +usages of it. */ > > + tree vdef; > > + /* This statement is to be moved. */ > > + if ((vdef = gimple_vdef (stmt))) > > + LOOP_VINFO_EARLY_BRK_CONFLICT_STMTS > (loop_vin

[no subject]

Greetings, I noticed you from LinkedIn? Can I share an idea on this email?

Re: [PATCH] RISC-V: Fix calculation of max live vregs

Hi juzhe, The live ranges are represented as [def_point, last_use_point] in code. For example: 0: _2 = _x1 + _x2 1: _3 = _y1 + _y2 2: _1 = _2 + _3 3: _4 = _1 + x1 Origin: live ranges: _1: [2, 3] _2: [0, 2] _3: [1, 2] _x1:[0, 3] max live regs calc: _1 _2 _3 _x1 0 x x 1 x

Re: Re: [PATCH] RISC-V: Fix calculation of max live vregs

I see. LGTM. Thanks for explanation. I will ask Li Pan commit it for you. Thanks. juzhe.zh...@rivai.ai From: Demin Han Date: 2023-12-20 19:10 To: juzhe.zh...@rivai.ai; gcc-patches CC: pan2.li Subject: Re: [PATCH] RISC-V: Fix calculation of max live vregs Hi juzhe, The live ranges are repres

[PATCH] Support libcall __float{, un}sibf by SF when it is not supported for _bf16

We don't have SI -> BF library functions, use SI -> SF -> BF instead. Although this can also be implemented in a target machine description, it is more appropriate to move into target independent code. gcc/ChangeLog: * optabs.cc (expand_float): Split SI -> BF into SI -> SF -> BF. --- gcc

RE: Re: [PATCH] RISC-V: Fix calculation of max live vregs

Committed, thanks all. Pan From: juzhe.zh...@rivai.ai Sent: Wednesday, December 20, 2023 7:18 PM To: demin.han ; gcc-patches Cc: Li, Pan2 Subject: Re: Re: [PATCH] RISC-V: Fix calculation of max live vregs I see. LGTM. Thanks for explanation. I will ask Li Pan commit it for you. Thanks. ___

[PATCH v3 0/6] RISC-V: Support XTheadVector extension

This patch series presents gcc implementation of the XTheadVector extension [1]. [1] https://github.com/T-head-Semi/thead-extension-spec/ For some vector patterns that cannot be avoided, we use "!TARGET_XTHEADVECTOR" to disable them in order not to generate instructions that xtheadvector does not

RE: [PATCH 3/21]middle-end: Implement code motion and dependency analysis for early breaks

On Wed, 20 Dec 2023, Tamar Christina wrote: > > > + /* If we've moved a VDEF, extract the defining MEM and update > > > + usages of it. */ > > > + tree vdef; > > > + /* This statement is to be moved. */ > > > + if ((vdef = gimple_vdef (stmt))) > > > + LO

[PATCH v3 1/6] RISC-V: Refactor riscv-vector-builtins-bases.cc

This patch moves the definition of the enums lst_type and frm_op_type into riscv-vector-builtins-bases.h and removes the static visibility of fold_fault_load(), so these can be used in other compile units. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (enum lst_type):

[PATCH v3 2/6] RISC-V: Split csr_operand in predicates.md for vector patterns.

This patch splits the definition of csr_operand in predicates.md. The newly defined vector_csr_operand has the same functionality as csr_operand but can only be used in vector patterns, so that changes for vector will not affect scalar patterns in files like riscv.md. gcc/ChangeLog: * con

[PATCH v3 3/6] RISC-V: Introduce XTheadVector as a subset of V1.0.0

This patch is to introduce basic XTheadVector support (march string parsing and a test for __riscv_xtheadvector) according to https://github.com/T-head-Semi/thead-extension-spec/ gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): Add new vendor extens

[PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

This patch adds th. prefix to all XTheadVector instructions by implementing new assembly output functions. gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_asm_output_opcode): New function. * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise. * config/ri

[PATCH v3 6/6] RISC-V: Add support for xtheadvector-specific intrinsics.

This patch only involves the generation of xtheadvector special load/store instructions and vext instructions. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class th_loadstore_width): Define new builtin bases. (BASE): Define new builtin bases. * con

[PATCH] Improve DCE of dead parts of a permute chain

gcc.dg/vect/bb-slp-pr78205.c is reported to have regressed with the PR113073 change and in the end it's due to the DCE performed by vect_transform_slp_perm_load_1 being imperfect. The following enhances it to also cover the CTOR and VIEW_CONVERT operations that might be involved. Bootstrapped and

Re: [PATCH] tree-optimization/113073 - amend PR112736 fix

On Wed, 20 Dec 2023, Richard Biener wrote: > On Wed, 20 Dec 2023, Thomas Schwinge wrote: > > > Hi! > > > > On 2023-12-19T13:30:58+0100, Richard Biener wrote: > > > The PR112736 testcase fails on RISC-V because the aligned exception > > > uses the wrong check. The alignment support scheme can b

No libstdc++ for GCN (was: No libstdc++ for nvptx)

Hi! On 2015-03-11T22:44:27+0100, I wrote: > I committed the following in r221362: > No libstdc++ for nvptx. > > The C++ front end insists to link against libstdc++ -- which we don't > build: > > $ < build-gcc/gcc/testsuite/g++/g++.log grep -o 'error opening > [^[:cntrl:]]*' | so

Re: veclower: improve selection of vector mode when lowering [PR 112787]

Thanks, fully agree with all comments. gcc/ChangeLog: PR target/112787 * tree-vect-generic (type_for_widest_vector_mode): Change function to use original vector type and check widest vector mode has at most the same number of elements. (get_compute_type)

Re: [PATCH] tree-optimization/113073 - amend PR112736 fix

Hi Richard! On 2023-12-20T14:44:29+0100, Richard Biener wrote: > On Wed, 20 Dec 2023, Richard Biener wrote: >> On Wed, 20 Dec 2023, Thomas Schwinge wrote: >> > On 2023-12-19T13:30:58+0100, Richard Biener wrote: >> > > The PR112736 testcase fails on RISC-V because the aligned exception >> > > use

Re: [PATCH 1/8] OpenMP: lvalue parsing for map/to/from clauses (C++)

On 05.09.23 21:28, Julian Brown wrote: This patch supports "lvalue" parsing (or "locator list item type" parsing) for several OpenMP clause types for C++, as required for OpenMP 5.0 and above. It is based on the version committed to the og13 branch, posted here: https://gcc.gnu.org/pipermail

Re: veclower: improve selection of vector mode when lowering [PR 112787]

On Wed, 20 Dec 2023, Andre Vieira (lists) wrote: > Thanks, fully agree with all comments. > > gcc/ChangeLog: > > PR target/112787 > * tree-vect-generic (type_for_widest_vector_mode): Change function > to use original vector type and check widest vector mode has at most >

Re: [PATCH] tree-object-size: Clean up unknown propagation

On 2023-12-20 00:23, Jeff Law wrote: On 12/19/23 10:21, Siddhesh Poyarekar wrote: Narrow down scope of the unknowns bitmap so that it is only accessible within the reexamination process.  This also removes any role of unknown propagation from object_sizes_set, thus simplifying that code path a

[PATCH] [OpenACC] Add tests for implied copy of variables in reduction clause.

From: Hafiz Abid Qadeer The OpenACC reduction clause on compute construct implies a copy clause for each reduction variable [1]. This patch adds tests to check if the implied copy is being generated. The check covers various types and operators as described in the specification. gcc/testsuite/Ch

omp: Fix simdclone arguments with veclen lower than simdlen [PR113040]

This patch fixes an issue introduced by: commit ea4a3d08f11a59319df7b750a955ac613a3f438a Author: Andre Vieira Date: Wed Nov 1 17:02:41 2023 + omp: Reorder call for TARGET_SIMD_CLONE_ADJUST The problem was that after this patch we no longer added multiple arguments for vector argument

Re: [PATCH] RISC-V: Fix calculation of max live vregs

On 12/20/23 04:17, juzhe.zh...@rivai.ai wrote: I see. LGTM. Thanks for explanation. I will ask Li Pan commit it for you. The patch from Demin didn't specify if it had been regression tested. All patches must be regression tested and an indication that the test passed and on what target mus

Re: Re: [PATCH] RISC-V: Fix calculation of max live vregs

Ok. Thanks Jeff reminding me. Will be carefull next time. juzhe.zh...@rivai.ai From: Jeff Law Date: 2023-12-20 23:28 To: juzhe.zh...@rivai.ai; demin.han; gcc-patches CC: pan2.li Subject: Re: [PATCH] RISC-V: Fix calculation of max live vregs On 12/20/23 04:17, juzhe.zh...@rivai.ai wrote: >

Re: [PATCH v26 00/23] Optimize type traits compilation performance

On Tue, 19 Dec 2023, Sandra Loosemore wrote: > On 12/6/23 22:11, Ken Matsui wrote: > > This patch series optimizes type traits compilation performance by > > implementing built-in type traits and using them in libstdc++. > > I'm finding that all the new g++.dg/ext/is_*.C testcases added by this p

Re: [PATCH v2 2/3] RISC-V: setmem for RISCV with V extension

On 12/20/23 02:48, Sergei Lewis wrote: Hi, This has been tested with the following configurations: rv64gcv_zvl128b rv64gcv_zvl256b rv32imafd_zve32x1p0 rv32gc_zve64f_zvl128b I'll drop the constraints and add the testing info to the cover email in v3. I'll hold off submitting v3 until gcc-15

Re: [PATCH 1/2] arm: Add define_attr to to create a mapping between MVE predicated and unpredicated insns

Reworked patch after Richard's comments and moved predicated_doloop_end_internal and dlstp*_insn to the next patch in the series to make sure this one builds on its own. On 18/12/2023 11:53, Andre Vieira wrote: Re-sending Stam's first patch, same as: https://gcc.gnu.org/pipermail/gcc-patches/

Re: [PATCH 2/2] arm: Add support for MVE Tail-Predicated Low Overhead Loops

Squashed the definition and changes to predicated_doloop_end_internal and dlstp*_insn into this patch to make sure the first patch builds independently On 18/12/2023 11:53, Andre Vieira wrote: Reworked Stam's patch after comments in: https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640

Re: [PATCH] c++: implicit guides should inherit class constraints [PR104873]

On Fri, 1 Apr 2022, Jason Merrill wrote: > On 4/1/22 11:17, Patrick Palka wrote: > > An implicit guide already inherits the (rewritten) constraints of the > > constructor. Thus it seems natural that the guide must also inherit > > the constraints of the class template, since a constructor's const

Re: [PATCH] RISC-V: Fix RISCV_FUSE_ZEXTWS fusion condition

On 12/20/23 01:39, Wang Pengcheng wrote: From: wangpc The condition is RISCV_FUSE_ZEXTH, which is a mistake. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix condition. Thanks! As soon as this patch finishes regression testing I'll push it to the trunk. I'm curiou

Re: [PATCH v26 00/23] Optimize type traits compilation performance

On Wed, Dec 20, 2023 at 7:56 AM Patrick Palka wrote: > > On Tue, 19 Dec 2023, Sandra Loosemore wrote: > > > On 12/6/23 22:11, Ken Matsui wrote: > > > This patch series optimizes type traits compilation performance by > > > implementing built-in type traits and using them in libstdc++. > > > > I'm

Re: [PATCH] compare_tests: distinguish c-c++-common results by tool

On 12/19/23 23:31, Alexandre Oliva wrote: On Dec 20, 2023, Jeff Law wrote: So the strub tests in c-c++-common are problematical. They get run twice, once for C, once for C++. Yet the name of the test is the same in both runs. (by the name, I mean the name emitted into the dejagnu summary

Re: [PATCH] c++: implicit guides should inherit class constraints [PR104873]

On 12/20/23 12:00, Patrick Palka wrote: On Fri, 1 Apr 2022, Jason Merrill wrote: On 4/1/22 11:17, Patrick Palka wrote: An implicit guide already inherits the (rewritten) constraints of the constructor. Thus it seems natural that the guide must also inherit the constraints of the class templat

[pushed] c++: xvalue array subscript [PR103185]

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- Normally we handle xvalue array subscripting with ARRAY_REF, but in this case we weren't doing that because the operands were reversed. Handle that case better. PR c++/103185 gcc/cp/ChangeLog: * typeck.cc (cp_build_array_

[pushed] c++: throwing dtor and empty try [PR113088]

Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- maybe_splice_retval_cleanup assumed that the function body can't be empty if there's a throwing cleanup, but when I added cleanups to try blocks in r12-6333-gb10e031458d541 I didn't adjust that assumption. PR c++/113088 PR c

Re: [PATCH] RISC-V: Fix RISCV_FUSE_ZEXTWS fusion condition

On 12/20/23 01:39, Wang Pengcheng wrote: The condition is RISCV_FUSE_ZEXTH, which is a mistake. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix condition. I've pushed this to the trunk. Attached is the actual patch committed which also fixes formatting of that code.

Re: [PATCH] RISC-V: Optimize SELECT_VL codegen when length is known as smaller than VF

On 12/19/23 23:55, Juzhe-Zhong wrote: While trying to fix bugs of PR113097, notice this following situation we generate redundant vsetvli _255 = SELECT_VL (3, POLY_INT_CST [4, 4]); COND_LEN (..., _255) Before this patch: vsetivli a5, 3... ... vadd.vv (use a5) After this patch: ... vadd.vv

Re: [PATCH] RISC-V: Fix bug of VSETVL fusion

On 12/19/23 23:50, Juzhe-Zhong wrote: This patch fixes bugs in the fusion of this following case: li a5,-1 vmv.s.x v0,a5 -> demand any non-zero AVL vsetvli a5, ... Incorrect fusion after VSETVL PASS: li a5,-1 vsetvli a5... vmv.s.x v0, a5 --> a5 is modified as incorrect value. We disallow t

Re: [PATCH] RISC-V: Block VLSmodes according to TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR

On Tue, 05 Dec 2023 04:57:27 PST (-0800), juzhe.zh...@rivai.ai wrote: This patch fixes ICE mentioned on PR112851 and PR112852. Actually these ICEs happens many times in full coverage testing. The ICE happens on: bug.c:84:1: internal compiler error: in partial_subreg_p, at rtl.h:3187 84 | }

Re: [RFC][V2] RISC-V: Support -mcmodel=large.

On 12/18/23 00:46, KuanLin Chen wrote: Hi Jeff, Sorry for this missing. I've removed riscv_asm_output_pool_epilogue because the pool beginning is always aligned from FUNCTION_BOUNDARY. Please find attached. Thank you. Thanks. I regression tested this on rv64gc without any issues and fixed

Re: [RFC][V2] RISC-V: Support -mcmodel=large.

On Wed, 20 Dec 2023 09:55:48 PST (-0800), jeffreya...@gmail.com wrote: On 12/18/23 00:46, KuanLin Chen wrote: Hi Jeff, Sorry for this missing. I've removed riscv_asm_output_pool_epilogue because the pool beginning is always aligned from FUNCTION_BOUNDARY. Please find attached. Thank you. Tha

[PATCH] RISC-V: Document -mcmodel=large

This slipped through the cracks. Probably also NEWS-worthy. gcc/ChangeLog: * doc/invoke.texi (RISC-V): Add -mcmodel=large. --- gcc/doc/invoke.texi | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 5af978b0a67..d8b35

Re: [RFC][V2] RISC-V: Support -mcmodel=large.

On 12/20/23 11:05, Palmer Dabbelt wrote: On Wed, 20 Dec 2023 09:55:48 PST (-0800), jeffreya...@gmail.com wrote: On 12/18/23 00:46, KuanLin Chen wrote: Hi Jeff, Sorry for this missing. I've removed riscv_asm_output_pool_epilogue because the pool beginning is always aligned from FUNCTION_BO

Re: [PATCH] RISC-V: Document -mcmodel=large

On 12/20/23 11:08, Palmer Dabbelt wrote: This slipped through the cracks. Probably also NEWS-worthy. gcc/ChangeLog: * doc/invoke.texi (RISC-V): Add -mcmodel=large. OK. And yes, I think we're going to need to to a new/changes update for the port as a whole as part of the gcc-14 pr

Re: [PATCH v3 1/6] RISC-V: Refactor riscv-vector-builtins-bases.cc

On 12/20/23 05:25, Jun Sha (Joshua) wrote: This patch moves the definition of the enums lst_type and frm_op_type into riscv-vector-builtins-bases.h and removes the static visibility of fold_fault_load(), so these can be used in other compile units. gcc/ChangeLog: * config/riscv/riscv

Re: [PATCH v3 2/6] RISC-V: Split csr_operand in predicates.md for vector patterns.

On 12/20/23 05:27, Jun Sha (Joshua) wrote: This patch splits the definition of csr_operand in predicates.md. The newly defined vector_csr_operand has the same functionality as csr_operand but can only be used in vector patterns, so that changes for vector will not affect scalar patterns in fil

[PATCH, wwwdocs] RISC-V: Add -mcmodel=large for GCC-14

This was just merged. Looks like we forgot to add any other NEWS items, so I've added the header as well. --- htdocs/gcc-14/changes.html | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html index 24e6409a..2a7432a7 100644

Re: [RFC][V2] RISC-V: Support -mcmodel=large.

On Wed, 20 Dec 2023 10:12:04 PST (-0800), jeffreya...@gmail.com wrote: On 12/20/23 11:05, Palmer Dabbelt wrote: On Wed, 20 Dec 2023 09:55:48 PST (-0800), jeffreya...@gmail.com wrote: On 12/18/23 00:46, KuanLin Chen wrote: Hi Jeff, Sorry for this missing. I've removed riscv_asm_output_pool

Re: [PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

On 12/20/23 05:32, Jun Sha (Joshua) wrote: This patch adds th. prefix to all XTheadVector instructions by implementing new assembly output functions. gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_asm_output_opcode): New function. * config/riscv/riscv.cc (riscv_a

Re: [PATCH] RISC-V: Document -mcmodel=large

On Wed, 20 Dec 2023 10:13:06 PST (-0800), jeffreya...@gmail.com wrote: > > > On 12/20/23 11:08, Palmer Dabbelt wrote: >> This slipped through the cracks. Probably also NEWS-worthy. >> >> gcc/ChangeLog: >> >> * doc/invoke.texi (RISC-V): Add -mcmodel=large. > OK. > > And yes, I think we're goin

Re: [RFC][V2] RISC-V: Support -mcmodel=large.

On 12/20/23 11:21, Palmer Dabbelt wrote: Yea, the implementation relies largely on just pushing stuff into the constant pool, so we're largely independent ABI stuff with the likely exception being relocations. Ya, but I think we'd only need the relocations if we were going to try relaxing

Re: [aarch64] PR111702 - ICE in insert_regs after interleave+zip1 vector initialization patch

Prathamesh Kulkarni writes: > Hi Richard, > For the test-case mentioned in PR111702, compiling with -O2 > -frounding-math -fstack-protector-all results in following ICE during > cse2 pass: > > test.c: In function 'foo': > test.c:119:1: internal compiler error: in insert_regs, at cse.cc:1120 > 11

[PATCH] cse: Fix handling of fake vec_select sets [PR111702]

If cse sees: (set (reg R) (const_vector [A B ...])) it creates fake sets of the form: (set R[0] A) (set R[1] B) ... (with R[n] replaced by appropriate rtl) and then adds them to the tables in the same way as for normal sets. This allows a sequence like: (set (reg R2) A) ...(reg R2

[PATCH] RISC-V: Add --with-cmodel configure-time argument

I couldn't find another way to set the default code model. gcc/ChangeLog: * config.gcc (RISC-V): Add --with-cmodel * config/riscv/riscv.h (TARGET_DEFAULT_CMODEL): Use TARGET_RISCV_DEFAULT_CMODEL --- I thought we had this already, but I figured I'd double-check my "ya, that

Re: [RFC][V2] RISC-V: Support -mcmodel=large.

On Wed, 20 Dec 2023 10:25:00 PST (-0800), jeffreya...@gmail.com wrote: On 12/20/23 11:21, Palmer Dabbelt wrote: Yea, the implementation relies largely on just pushing stuff into the constant pool, so we're largely independent ABI stuff with the likely exception being relocations. Ya, but I

Re: [PATCH 1/3][RFC] RISC-V: Add non-vector types to pipelines

On 12/15/23 11:53, Edwin Lu wrote: This patch does not create vector related insn reservations for generic.md and sifive-7.md. It updates/creates insn reservations for all non-vector typed insns gcc/ChangeLog: * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): create/update reserv

Re: [PATCH 2/3][RFC] RISC-V: Add vector related reservations

On 12/15/23 11:53, Edwin Lu wrote: This patch copies the vector reservations from generic-ooo.md and inserts them into generic.md and sifive.md. The vector pipelines are necessary to avoid an ICE from the assert gcc/ChangeLog: * config/riscv/generic-ooo.md: syntax * config

Re: [PATCH 3/3][RFC] RISC-V: Enable assert for insn_has_dfa_reservation

On 12/15/23 11:53, Edwin Lu wrote: Enables assert that every typed instruction is associated with a dfa reservation gcc/ChangeLog: * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert Once the prereqs are in, this is fine. jeff

Re: [PATCH] cse: Fix handling of fake vec_select sets [PR111702]

> Am 20.12.2023 um 19:30 schrieb Richard Sandiford : > > If cse sees: > > (set (reg R) (const_vector [A B ...])) > > it creates fake sets of the form: > > (set R[0] A) > (set R[1] B) > ... > > (with R[n] replaced by appropriate rtl) and then adds them to the tables > in the same way as

[PATCH] testsuite: Remove testsuite_tr1.h

This patch removes the testsuite_tr1.h dependency from g++.dg/ext/is_*.C tests since the header is supposed to be used only by libstdc++, not front-end. This also includes test code consistency fixes. gcc/testsuite/ChangeLog: * g++.dg/ext/is_array.C: Remove testsuite_tr1.h. Add necessar

[PATCH] c++: Enable -Walloc-size and -Wcalloc-transposed-args warnings for C++

Hi! The following patch enables the -Walloc-size and -Wcalloc-transposed-args warnings for C++ as well. Ok for trunk if it passes bootstrap/regtest? 2023-12-20 Jakub Jelinek gcc/c-family/ * c.opt (Walloc-size): Enable also for C++ and ObjC++. gcc/cp/ * cp-gimplify.cc (cp_gene

Re: Fortran: Use non conflicting file extensions for intermediates [PR81615]

Am 20.12.23 um 05:32 schrieb Rimvydas Jasinskas: Dear all, In the spirit of c/c++ using the .i/.ii extensions for intermediates, use the .fi/.fii intermediate extensions for gfortran fixed/free form sources when -save-temps is invoked to avoid various issues. I checked with Jerry on Mattermost

Re: [PATCH] sel-sched: Verify change before replacing dest in EXPR_INSN_RTX [PR112995]

On 12/15/23 01:52, Kewen.Lin wrote: Hi, PR112995 exposed one issue in current try_replace_dest_reg that the result rtx insn after replace_dest_with_reg_in_expr is probably unable to match any constraints. Although there are some checks on the changes onto dest or src of orig_insn, none is pe

Re: [pushed][PR112918][LRA]: Fixing IRA ICE on m68k

On Mon, 18 Dec 2023, Jeff Law wrote: > > > On 12/18/23 15:16, Vladimir Makarov wrote: > > The following patch fixes > > > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112918 > > > > The patch was successfully bootstrapped and tested on x86-64, aarch64, and > > ppc64. > > > > The patch affec

Re: PING^1 [PATCH] sched: Remove debug counter sched_block

On 12/11/23 23:17, Kewen.Lin wrote: Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636597.html BR, Kewen on 2023/11/15 17:01, Kewen.Lin wrote: Hi, on 2023/11/10 01:40, Alexander Monakov wrote: I agree with the concern. I hoped that solving the problem by

Re: [RFC][V2] RISC-V: Support -mcmodel=large.

On 12/20/23 10:41, Palmer Dabbelt wrote: On Wed, 20 Dec 2023 10:25:00 PST (-0800), jeffreya...@gmail.com wrote: On 12/20/23 11:21, Palmer Dabbelt wrote: Yea, the implementation relies largely on just pushing stuff into the constant pool, so we're largely independent ABI stuff with the like

Re: [PATCH v7 5/5] OpenMP/OpenACC: Reorganise OMP map clause handling in gimplify.cc

Hi Tobias, Thanks for review! Here's a new version of the patch which hopefully addresses this round of comments. On Tue, 19 Dec 2023 16:41:54 +0100 Tobias Burnus wrote: > On 16.12.23 14:25, Julian Brown wrote: > > --- a/gcc/gimplify.cc > > +++ b/gcc/gimplify.cc > > @@ -10107,6 +10114,20 @@ omp

[PATCH] c++: fix -Wparentheses with boolean-like class types

Bootstrap and regtesting in progress on x86_64-pc-linux-gnu, does this look OK for trunk if successful? -- >8 -- Since r14-4977-g0f2e2080685e75 the -Wparentheses warning now undesirably warns on the idiom Wparentheses-34.C:9:14: warning: suggest parentheses around assignment used as truth value

Re: [PATCH 1/3][RFC] RISC-V: Add non-vector types to pipelines

On 12/20/2023 10:50 AM, Jeff Law wrote: On 12/15/23 11:53, Edwin Lu wrote: This patch does not create vector related insn reservations for generic.md and sifive-7.md. It updates/creates insn reservations for all non-vector typed insns gcc/ChangeLog: * config/riscv/generic-ooo.md (generic

[PATCH] aarch64: Prevent moving throwing accesses in ldp/stp pass [PR113093]

As the PR shows, there was nothing to prevent the ldp/stp pass from trying to move throwing insns, which lead to an RTL verification failure. This patch fixes that. Bootstrapped/regtested on aarch64-linux-gnu, OK for trunk? Thanks, Alex gcc/ChangeLog: PR target/113093 * config/

Re: [PATCH] c++: fix -Wparentheses with boolean-like class types

On 12/20/23 17:07, Patrick Palka wrote: Bootstrap and regtesting in progress on x86_64-pc-linux-gnu, does this look OK for trunk if successful? -- >8 -- Since r14-4977-g0f2e2080685e75 the -Wparentheses warning now undesirably warns on the idiom Wparentheses-34.C:9:14: warning: suggest parenthe

Re: Re: [PATCH] RISC-V: Block VLSmodes according to TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR

I was thinking the commit log is quite clear but I don't mind telling you more details behind this patch. First, This patch is not an optimization patch, is fatal ICE and run-time bug fix patch as commit log said. Before this patch, we enable more aggressive VLSmodes that size larger than MAX_

Re: [PATCH] c++: Enable -Walloc-size and -Wcalloc-transposed-args warnings for C++

On 12/20/23 14:20, Jakub Jelinek wrote: Hi! The following patch enables the -Walloc-size and -Wcalloc-transposed-args warnings for C++ as well. Ok for trunk if it passes bootstrap/regtest? 2023-12-20 Jakub Jelinek gcc/c-family/ * c.opt (Walloc-size): Enable also for C++ and ObjC++.

Re: Re: [PATCH v3 4/6] RISC-V: Adds the prefix "th." for the instructions of XTheadVector.

>> So rather than looking at the mode, would it make more sense to have an >> attribute (or re-use an existing attribute) to identify which opcodes >> are going to need prefixing? We've got access to the INSN via >> current_output_insn. So we can lookup attributes trivially. Yes, I totally aggre

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